3D NAND Memory Pillar Structure for Faster Non-Volatile Storage
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Solution Overview
Problem
Existing NAND flash memory technologies face challenges in efficiently storing and retrieving data in a non-volatile manner due to limitations in memory cell design and operation efficiency.
Innovation Solution
A semiconductor memory device with a specific configuration and circuit design, including a memory cell array, row decoder module, and sense amplifier module, that utilizes a NAND-type flash memory structure with optimized conductive layers and pillars to enhance data storage and retrieval capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional NAND flash memory cell design is used, then data storage capability is maintained, but data storage efficiency and operational performance are limited
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to vertical 3D stacking architecture, where multiple memory cell layers are stacked along the vertical direction. This dimensional change increases storage density without proportionally increasing device footprint, thereby improving data storage efficiency while managing design complexity through modular layer construction.
Solution Approach 2:
The memory device is divided into multiple independent memory cell layers stacked vertically, with each layer containing complete memory cell structures including semiconductor layers, insulating layers, and conductive layers. This segmentation allows parallel processing and independent optimization of each layer, improving overall storage efficiency while maintaining manageable complexity through standardized repeating units.
2Ease of manufacture
If memory cell structure is simplified, then manufacturing becomes easier, but data storage capability and operational performance deteriorate
Solution Approach 1:
The patent modifies physical parameters of the memory cell structure, including the thickness and material composition of insulating layers (such as tunnel insulating layers and block insulating layers), the doping concentrations of semiconductor layers, and the geometry of conductive layers. These parameter optimizations enable reliable data storage while maintaining manufacturability through standardized process parameters.
Solution Approach 2:
The memory cell employs composite material structures, including stacked insulating layers with different dielectric properties (tunnel insulating layer, block insulating layer), semiconductor layers with varying doping types and concentrations, and conductive layers with different resistivity characteristics. This composite approach achieves reliable data storage functionality while allowing each material layer to be optimized for its specific function, balancing performance and manufacturability.
Data Source
AI summary
A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.