3D NAND Memory Cell Layout for Reduced Planar Footprint
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Solution Overview
Problem
Existing three-dimensional NAND flash memories have a large planar size due to the arrangement of memory cells, which limits their integration density.
Innovation Solution
The solution involves forming channel stacks separately along one side of the gate stacks and electrically connecting upper conductive layers to the crossed channel stacks, reducing the planar size of the memory cell by optimizing the arrangement and connection of the channel and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel stacks are arranged on both sides of gate stacks with shared bit lines, then device integration is improved, but manufacturing complexity increases due to precise alignment requirements
Solution Approach 1:
The patent divides the memory cell structure into separate components: gate stacks arranged in a first direction and channel stacks arranged in a second direction orthogonal to the first. This segmentation allows independent formation and simplifies manufacturing by eliminating the need for complex shared bit line connections, while still achieving high device integration through the orthogonal arrangement.
Solution Approach 2:
The patent transitions from a planar arrangement where channel stacks are positioned on both sides of gate stacks to a three-dimensional orthogonal arrangement. By positioning channel stacks in a direction orthogonal to the gate stacks and using strip-shaped upper conductive layers extending in the orthogonal direction, the patent achieves higher integration density while simplifying the connection architecture.
2Ease of manufacture
If conventional memory cell arrangement is used, then manufacturing is simpler, but planar size is large reducing integration density
Solution Approach 1:
The patent employs a three-dimensional orthogonal arrangement where gate stacks extend in a first direction and channel stacks extend in a second direction orthogonal to the first. This vertical stacking and orthogonal arrangement significantly reduces the planar footprint of each memory cell compared to conventional two-dimensional layouts, achieving higher integration density while maintaining manufacturing feasibility through standardized fabrication processes.
Solution Approach 2:
The patent creates a modular memory cell structure where the orthogonal arrangement of gate stacks and channel stacks with strip-shaped upper conductive layers serves multiple functions: it reduces planar size for higher integration, simplifies the connection architecture compared to shared bit lines, and maintains compatibility with existing manufacturing processes. This universal structure can be scaled and adapted for various integration densities.
Data Source
AI summary
A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.