3D NAND Memory Pre-Programming Voltage Control
Solution Overview
Problem
Existing memory devices face challenges in preventing over-erasure during repetitive erase operations, leading to deterioration of memory cells and reduced retention characteristics, as they lack a method to individually adjust pre-programming voltages based on the operating characteristics of memory cells in a 3D memory array.
Innovation Solution
A memory device and system that includes a control logic to generate pre-programming control signals for varying pre-programming voltages applied to word lines in a 3D memory array, taking into account the distance of each word line from the substrate and the operating characteristics of memory cells, to prevent over-erasure before performing an erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform pre-programming voltage is applied to all word lines before erase operation, then the erase operation can be performed uniformly across the memory array, but memory cells at different word lines experience different stress levels leading to over-erasure and deterioration
Solution Approach 1:
The patent applies different pre-programming voltages to different word lines based on their position in the memory array. Word lines closer to the substrate receive different voltage levels than those farther away, compensating for the varying stress levels and preventing over-erasure in specific regions while maintaining overall erase effectiveness.
Solution Approach 2:
The patent modifies the pre-programming voltage parameter dynamically based on the word line position and memory cell operating characteristics. By adjusting voltage levels according to location, the system optimizes the balance between erase effectiveness and memory cell protection without requiring complete operational redesign.
2Productivity
If repetitive erase operations are performed without pre-programming, then the memory device can be efficiently erased, but memory cells deteriorate and retention characteristics are reduced
Solution Approach 1:
The patent performs a pre-programming operation before the erase operation to prepare the memory cells. This preliminary action adjusts the threshold voltages of memory cells based on their position, creating a more uniform stress distribution during the subsequent erase operation and preventing over-erasure that would lead to cell deterioration.
Solution Approach 2:
The pre-programming step acts as a cushioning mechanism that protects memory cells from excessive stress during erase operations. By pre-adjusting the voltage states of memory cells according to their location, the system reduces the harmful effects of repetitive erasing and maintains better retention characteristics over time.
3Manufacturing precision
If position-based voltage adjustment is implemented, then over-erasure is prevented and memory cell characteristics are compensated, but the control mechanism becomes more complex
Solution Approach 1:
The patent divides the memory array into different regions or groups based on word line position, applying different pre-programming voltage levels to each segment. This segmentation approach simplifies the control logic compared to individually addressing each memory cell, while still achieving the goal of position-based compensation for over-erasure.
Data Source
AI summary
A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.