3D NAND Memory Program Disturb Mitigation via Pre-Charge Voltage Control
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Solution Overview
Problem
In 3D NAND memory devices, program disturb occurs due to residual electrons trapped in storage regions of unselected memory strings, which can lead to unintended programming of unselected memory cells, especially in dual-deck structures, where the channel turn-off effect makes it difficult to remove accumulated charges effectively during the programming phase.
Innovation Solution
A method and memory device configuration that includes applying specific voltage signals during the pre-charging and programming phases to manage the channel potential of unselected memory strings, using a word line driver to apply varying voltages to word lines and bit lines, ensuring residual electrons are removed from unselected strings to prevent program disturb. This involves applying a voltage to all top memory cells during the pre-charging phase to attract and then cut off residual electrons from the channels, forming a stepwise channel potential to discharge trapped electrons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programming operation is performed in 3D NAND memory devices, then programming speed is maintained, but program disturb occurs due to residual electrons trapped in storage regions of unselected memory strings
Solution Approach 1:
The patent applies a preliminary action by performing a pre-charge operation before the actual programming phase. During this pre-charge phase, a first voltage signal is applied to word lines coupled to first memory cells, and a second voltage signal is applied to bit lines, which attracts residual electrons from unselected memory strings to designated storage regions. This preliminary electron redistribution prevents program disturb during the subsequent programming operation, thereby improving programming accuracy without sacrificing speed.
2Reliability
If voltage signals are applied to remove residual electrons from unselected strings, then program disturb is reduced, but control circuit complexity increases
Solution Approach 1:
The patent implements local quality by applying different voltage signals to different parts of the memory array during the pre-charge phase. Specifically, word lines coupled to first memory cells receive a first voltage signal, while word lines coupled to second memory cells receive a third voltage signal, and bit lines receive a second voltage signal. This localized voltage application strategically manages electron distribution in specific regions without requiring complex global control, thereby reducing control circuit complexity while maintaining programming accuracy.
3Reliability
If channel potential is managed during programming phase, then residual electrons are removed from unselected strings, but programming operation complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory string into two distinct parts: first memory cells with storage regions and second memory cells without storage regions. During the pre-charge phase, voltage signals are applied specifically to word lines coupled to first memory cells to attract residual electrons to their storage regions. During the programming phase, voltage signals are applied to word lines coupled to second memory cells to manage channel potential and prevent electron trapping. This segmentation allows independent control of electron management and programming operations, reducing overall operation complexity while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces program disturb by removing residual electrons from unselected memory strings, improving the accuracy of programming operations and reducing the complexity of the control circuit logic, thereby enhancing the reliability and efficiency of memory device operations.
Implementation Method 1
applying a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase prior to a programming phase
Data Source
AI summary
A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.