3D QLC NAND Memory Programming with Position-Dependent Verify Currents
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Solution Overview
Problem
The existing coarse/fine programming method for 3D QLC NAND memory devices has a small margin on threshold voltages due to increasing differences between best-of-current and worse-of-current case current-voltage curves as the number of layers increases, leading to larger gain variations among memory cells.
Innovation Solution
A method involving multiple coarse programming steps with varying coarse verify currents, followed by fine programming and verification, to adjust the voltage difference between coarse and fine verify operations, ensuring consistent programming across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in 3D QLC NAND memory device is increased, then storage capacity is improved, but gain variations among memory cells increase leading to smaller threshold voltage margin
Solution Approach 1:
The patent applies different verify currents to different word lines based on their position in the stack. Word lines closer to the source use higher verify currents while those closer to the drain use lower verify currents. This local differentiation compensates for the position-dependent gain variations that occur in multi-layer 3D QLC NAND memory devices, thereby maintaining adequate threshold voltage margins across all memory cells despite increased layer count.
Solution Approach 2:
The patent dynamically adjusts the verify current parameter based on word line position and programming state. By changing the verify current magnitude according to the specific word line being verified and the current programming progress, the system compensates for the increasing gain variations that result from having more layers, thus maintaining reliable threshold voltage margins throughout the stack.
2Device complexity
If constant coarse/fine verify current is used in prior art method, then verification process is simplified, but threshold voltage margin becomes small due to gain variations
Solution Approach 1:
Instead of using a single constant verify current for all word lines, the patent implements position-dependent verify currents where each word line receives a tailored current level based on its location in the stack. This resolves the contradiction by accepting increased process complexity (multiple current levels) to achieve the necessary reliability (adequate threshold voltage margin) in multi-layer devices.
Solution Approach 2:
The verify current is made dynamic rather than static, adjusting according to word line position and programming state. This dynamic adjustment allows the verification process to adapt to the varying characteristics of different word lines in the stack, maintaining adequate margins without requiring overly complex fixed multi-level current schemes.
3Productivity
If coarse and fine programming steps are used, then programming speed is improved, but verification requires multiple current levels increasing process complexity
Solution Approach 1:
The patent employs dynamic verify current selection that adapts to the programming state and word line position. During coarse programming phases, higher verify currents are used for faster verification, while during fine programming phases, lower verify currents suffice. This dynamic approach maintains high programming speed while avoiding the need for permanently complex multi-level verify current infrastructure.
Solution Approach 2:
The verification process is segmented into different phases (coarse and fine) with different current requirements. By dividing the programming and verification process into segments, each with appropriate verify current levels, the system achieves high overall programming speed while managing verification complexity through phased rather than simultaneous multi-level current requirements.
Data Source
AI summary
When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.