3D NAND In-Memory Encryption Using PUF-Based Codec Keys
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Solution Overview
Problem
Existing data encryption and decryption technologies in memory devices face challenges in implementing efficient encryption and decryption methods that utilize physically unclonable function (PUF) technology without storage overhead, particularly in high-capacity and high-performance integrated circuit memories like 3D NAND flash memory.
Innovation Solution
A device and method for encryption and decryption are implemented using a memory array with memory strings, bit-line voltage suppliers, and a memory controller, employing XOR/XNOR operations based on codec keys generated from PUF data, allowing for large-scale parallelism and fine-grained data encoding/decoding without storing the PUF data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data encryption and decryption technology is implemented in memory devices, then data security is improved, but device complexity increases
Solution Approach 1:
The memory device is designed to perform both data storage and encryption/decryption operations using the same memory strings and sensing circuits. The memory controller executes software-based cryptographic algorithms, allowing the memory device to universally handle both storage and security functions without requiring separate dedicated encryption hardware, thereby improving data security while minimizing additional device complexity
Solution Approach 2:
The memory device utilizes its own internal resources (memory strings, sensing circuits, and controller) to perform encryption and decryption operations on data stored within itself. The memory controller executes cryptographic algorithms directly on the stored data, enabling the device to securely process its own data without external intervention, thus enhancing security while avoiding the need for additional external encryption components
2Reliability
If PUF technology is used to generate codec keys without storage, then security is improved, but implementation difficulty increases
Solution Approach 1:
The patent introduces a software-based key generation mechanism that acts as an intermediary between the physical memory device and the cryptographic security requirements. The memory controller executes software algorithms that generate and manage codec keys dynamically, serving as a mediator that translates physical memory operations into secure cryptographic functions without requiring complex hardware PUF integration, thus improving security while maintaining ease of manufacture
Solution Approach 2:
The system dynamically changes operational parameters (such as applying different voltages to memory strings during read operations) to enable the memory cells to function as temporary storage for cryptographic key bits during encryption/decryption operations. By changing the voltage states and timing parameters of existing memory components, the system generates and uses codec keys without requiring permanent storage infrastructure, improving security while avoiding additional manufacturing complexity
3Productivity
If existing hardware structure is used for XOR/XNOR operations, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the cryptographic operation into discrete segments that map directly to existing memory string operations. Each bit of the codec key and input data is processed through separate memory string read operations, with results combined through software-based XOR/XNOR logic. This segmentation allows the system to achieve high cryptographic processing productivity by parallelizing operations across multiple memory strings while using standard manufacturing processes for the individual memory components, thereby improving productivity without demanding excessive manufacturing precision
Data Source
AI summary
Disclosed are a device for encryption and decryption and a method for processing data. The device may be implemented by a memory device with a three-dimensional NAND flash memory with high capacity and high performance. The device includes a memory array, a data-sensing circuit, and a memory controller. A memory block in the memory array includes a first memory string with a first bit-line and a second memory string with a second bit-line. The memory controller is configured to: obtain a codec key, wherein memory cells in a first memory sub-area are set according to the codec key, and memory cells in a second memory sub-area are programed according to a complementary codec key; generate bit-line voltages of the first and the second bit-lines according to an input data; bias the memory cells in the first and the second memory sub-areas; and, obtain an output data according to the data-sensing circuit.