3D NAND Read Voltage Control for Adjacent Cell Disturbance
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Solution Overview
Problem
Scaling of planar memory cells in memory devices faces challenges due to process technology limitations and reliability issues, limiting storage density and performance in two-dimensional NAND memory devices.
Innovation Solution
A three-dimensional NAND memory device architecture with optimized read operations, where a peripheral circuit applies adjusted pass and read voltages to selected and unselected word lines to ensure accurate switching and minimize read disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high pass voltage is applied to unselected word lines to ensure switching on, then all unselected memory cells can be reliably activated, but read disturbance to adjacent memory cells increases and read margin deteriorates
Solution Approach 1:
The patent applies different pass voltages to different unselected word lines based on their position relative to the selected word line. Specifically, a first pass voltage is applied to unselected word lines adjacent to the selected word line, while a second pass voltage (lower than the first) is applied to other unselected word lines. This localized differentiation reduces read disturbance to adjacent memory cells while maintaining reliable switching on of unselected cells, directly resolving the contradiction between switching reliability and read disturbance.
2Quantity of substance
If planar memory cell scaling continues to increase storage density, then manufacturing cost decreases and storage capacity increases, but process technology limitations and reliability issues arise
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell scaling to three-dimensional vertically stacked memory cell architecture. By stacking multiple memory cell layers vertically, the patent achieves higher storage density without further scaling the planar dimensions, thereby avoiding the process technology limitations and reliability issues associated with continued planar scaling. This dimensional transition enables continued capacity growth while maintaining manufacturing feasibility and device reliability.
Data Source
AI summary
The present disclosure provides a memory device that includes memory cells addressed by word lines and bit lines and a peripheral circuit for performing a read operation for the memory device. The peripheral circuit is configured to apply a read voltage to a selected word line and apply a pass voltage to an unselected word line adjacent to the selected word line, wherein a magnitude of the pass voltage is adjusted according to the read voltage applied to the selected word line.