3D NAND Read Voltage Segmentation for Interference Correction
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Solution Overview
Problem
Three-dimensional NAND type flash memory devices face challenges in accurately reading data due to interference between adjacent memory cell transistors, leading to reading errors, especially when memory strings extend horizontally.
Innovation Solution
A nonvolatile semiconductor storage device configuration that includes a method for performing a read operation by selectively turning on and off specific select transistors and applying varying read voltages to the word line, allowing for accurate data determination by minimizing interference between memory cell transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory strings are arranged horizontally in three-dimensional NAND type flash memory to increase capacity, then storage density is improved, but interference between adjacent memory cell transistors increases leading to reading errors
Solution Approach 1:
The read operation is segmented into multiple phases with different voltage applications. First, a read voltage is applied to the word line while select transistors are turned off to read the target memory cell. Then, compensation read operations are performed with select transistors turned on to measure and correct interference effects. This segmentation allows separate measurement and correction of interference, improving reading accuracy in high-density horizontal arrangements.
Solution Approach 2:
The patent changes the voltage parameters dynamically during the read operation. Different voltage levels are applied to the word line (e.g., 0V, 3.3V, 5V) depending on the read phase and the state of select transistors. This parameter variation enables differentiation between the target cell signal and interference signals, allowing accurate data retrieval despite adjacent cell interference in high-capacity configurations.
2Speed
If read voltage is continuously applied to the word line, then reading speed is improved, but interference between adjacent memory cell transistors increases causing reading errors
Solution Approach 1:
The read operation uses periodic voltage pulses instead of continuous voltage application. The read voltage is applied in discrete phases: first phase with select transistors off for target cell reading, second phase with select transistors on for interference measurement. This periodic action reduces cumulative interference while maintaining adequate reading speed through optimized pulse timing and duration.
Data Source
AI summary
A nonvolatile semiconductor storage device includes a first channel layer including a first drain-side select transistor, a first source-side select transistor, and a first memory cell transistor, a second channel layer including a second drain-side select transistor, a second source-side select transistor, and a second memory cell transistor, a word line that functions as a gate electrode of the first and second memory cell transistors, and a controller. When a read operation is executed on the first memory cell transistor, the controller turns on the second drain-side select transistor and the second source-side select transistor, supplies a first voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and then, supplies a second voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned on.