3D NAND Read Setup Burst Command for Voltage Threshold Deviation
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Solution Overview
Problem
NAND flash memory experiences voltage threshold deviations over time, leading to unintended changes in logical states of cells, which existing error correcting codes can only partially address.
Innovation Solution
Implementing a read setup burst command to reduce voltage threshold deviation by performing read setup operations on sequential blocks, skipping bad blocks and using queues to identify candidate blocks that have not been accessed recently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read setup operations are performed on individual blocks, then voltage threshold deviation can be reduced, but processing time increases
Solution Approach 1:
The patent combines multiple individual read setup operations into a single burst operation that processes multiple sequential blocks simultaneously. The controller issues a read setup burst command that identifies a first block address and a number of blocks, causing the memory device to perform read setup operations on all specified blocks in one unified operation, thereby reducing total processing time while maintaining voltage threshold stability.
Solution Approach 2:
The patent performs read setup operations as preliminary actions before actual read operations are needed. By proactively conditioning memory blocks through read setup burst operations, the system prevents voltage threshold deviation before it affects data integrity, ensuring reliable reads without incurring corrective delays later.
2Reliability
If read setup operations are performed on all blocks, then voltage threshold deviation is reduced, but unnecessary operations on already-accessed blocks increase processing overhead
Solution Approach 1:
The patent applies read setup operations selectively to specific blocks that need conditioning rather than uniformly to all blocks. The system identifies candidate blocks based on characteristics such as sequential access patterns or blocks that have not been recently accessed, applying read setup operations only to those local areas where voltage threshold stability is needed, thereby avoiding unnecessary operations on already-conditioned blocks.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing burst mode operations with configurable block counts and address ranges. This allows dynamic adjustment of read setup operations based on actual memory access patterns and voltage threshold stability requirements, optimizing the balance between reliability and processing efficiency.
Data Source
AI summary
A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.