3D NAND Memory Structure for Channel and Low-Resistance Region Separation
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Solution Overview
Problem
Forming separate channel formation and low-resistance regions in three-dimensional NAND memory elements using metal oxides as semiconductor layers is challenging due to the inherent properties of metal oxides, where low-carrier-density regions function as channels and high-carrier-density regions as low-resistance areas.
Innovation Solution
A semiconductor device structure incorporating multiple insulators and conductors is designed, where a tunnel current is induced between the semiconductor surface and a charge-accumulating insulator by applying a potential to a conductor, with specific configurations and materials like silicon and metal oxides to manage oxygen concentration and resistance regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal oxide is used for a semiconductor layer in a three-dimensional NAND memory element, then the inherent properties of metal oxides allow low-carrier-density regions to function as channel formation regions and high-carrier-density regions to function as low-resistance regions, but it becomes challenging to form separate channel formation and low-resistance regions
Solution Approach 1:
The semiconductor layer is divided into multiple regions with different carrier densities. A first region is formed with a first carrier density to serve as the channel formation region, while a second region is formed with a second carrier density to serve as the low-resistance region. This segmentation allows distinct functional zones within the metal oxide semiconductor layer, resolving the challenge of creating separate channel and low-resistance regions while maintaining the inherent properties of metal oxides.
2Reliability
If multiple insulators and conductors are incorporated to manage oxygen concentration and resistance regions, then channel and low-resistance regions can be effectively formed and managed, but the device structure becomes more complex
Solution Approach 1:
Different regions of the semiconductor device are assigned different local properties through selective formation of insulator layers and conductor layers. The first insulator layer is formed in contact with the first region to control oxygen concentration in the channel formation region, while the second insulator layer is formed in contact with the second region to control oxygen concentration in the low-resistance region. Conductor layers are selectively positioned to provide electrical connections. This local quality approach enables precise control of electrical properties in different regions while managing the overall device complexity through functional specialization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of a novel semiconductor device with improved data capacity and reliability by effectively forming and managing channel and low-resistance regions within the memory element, enhancing the performance and efficiency of three-dimensional NAND memory elements.
Implementation Method 1
A tunnel current is induced between the second surface of the first semiconductor and the third insulator with the second insulator therebetween by supply of a potential to the second conductor
Data Source
AI summary
A semiconductor device with large memory capacity is provided. A semiconductor device includes first to fourth insulators, a first conductor, a second conductor, and a first semiconductor, and the first semiconductor includes a first surface and a second surface. A first side surface of the first conductor is included on the first surface of the first semiconductor, and a first side surface of the first insulator is included on a second side surface of the first conductor. The second insulator is included in a region including a second side surface and a top surface of the first insulator, a top surface of the first conductor, and the second surface of the first semiconductor. The third insulator is included on a formation surface of the second insulator, and the fourth insulator is included on a formation surface of the third insulator. The second conductor is included in a region overlapping the second surface of the first semiconductor in a region where the fourth insulator is formed. The third insulator has a function of accumulating charge. A tunnel current is induced between the second surface of the first semiconductor and the third insulator with the second insulator therebetween by supply of a potential to the second conductor.