3D NAND Memory Array Layout With Rounded Gates and Lower Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory cell designs and array architectures, particularly in NAND memory arrays, face challenges in optimizing performance and efficiency, especially in three-dimensional configurations.
Innovation Solution
The development of memory arrays with vertically-stacked conductive segments featuring rounded-nose transistor gates and specific material compositions, including charge-blocking and charge-storage materials, to enhance data storage capabilities and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory cell designs are used in NAND memory arrays, then manufacturing simplicity is maintained, but data storage efficiency and performance are insufficient
Solution Approach 1:
The patent transitions from planar memory cell architecture to three-dimensional vertically-stacked architecture. Memory cells are arranged in vertical columns extending through multiple tiers, with conductive segments stacked vertically rather than laid out in two-dimensional planes. This dimensional change dramatically increases storage density while maintaining manufacturing feasibility through established vertical deposition and etching processes.
Solution Approach 2:
The memory array is segmented into multiple tiers with distinct functional layers. Each tier contains charge-storage material, charge-blocking material, and conductive segments that are vertically stacked and laterally separated. This segmentation allows independent optimization of each layer's properties while maintaining overall array functionality, improving both storage efficiency and manufacturability.
2Object-generated harmful factors
If standard conductive segments are used, then manufacturing process simplicity is maintained, but parasitic capacitance in wordlines is excessive
Solution Approach 1:
The conductive segments are engineered with non-uniform cross-sectional areas along their vertical extent. Specific regions of the conductive segments have reduced dimensions to minimize parasitic capacitance formation, while other regions maintain sufficient dimensions for proper electrical connectivity. This local variation in geometry optimizes electrical performance without requiring complete redesign of the fabrication process.
3Quantity of substance
If vertically-stacked memory cells are implemented, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps that define the horizontal positions of vertical structures before vertical deposition. Template layers and alignment markers are formed in advance to guide subsequent vertical stacking operations. This preliminary structuring ensures that vertically-stacked memory cells align properly across multiple tiers, achieving high storage density while maintaining manufacturing precision through staged process control.
Data Source
AI summary
Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.