3D NAND Memory Stacking via Sacrificial Layer Removal
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Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, leading to the development of three-dimensional structures, but existing manufacturing methods for these devices face challenges in achieving reliable and efficient stacking of memory cells and interlayer structures.
Innovation Solution
A manufacturing method involving the formation of sacrificial layers and polysilicon spacers to create a stacked structure with alternating material layers, allowing for the formation of channel layers and memory cells with improved structural stability and reliability, while simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional non-volatile memory device structure is used, then manufacturing process is simple, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional stacked structure by forming multiple memory cell layers vertically over the substrate. This is achieved by creating alternating stacks of channel layers, barrier layers, and sacrificial layers, then forming memory layers around the channel layers in a vertical configuration, thereby increasing integration density while maintaining manufacturing feasibility through systematic layering processes
2Quantity of substance
If three-dimensional stacked structure is formed to increase integration density, then memory cell stacking is improved, but structural stability and manufacturing reliability deteriorate
Solution Approach 1:
The patent divides the three-dimensional stacked structure into multiple discrete layers including channel layers, barrier layers, and sacrificial layers that are formed alternately. Each layer is independently formed and controlled, allowing for precise thickness control and material selection. This segmentation enables the complex 3D structure to be manufactured layer-by-layer with improved structural stability and reduced manufacturing variability
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that facilitate the formation of the final memory device architecture. These sacrificial layers are formed between the channel layers and barrier layers, serve as placeholders during manufacturing, and are subsequently removed to create the desired void spaces or contact regions. This intermediary approach enables complex 3D structures to be built with improved reliability by using temporary supporting structures
3Quantity of substance
If three-dimensional stacked structure is formed to increase integration density, then memory cell stacking is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs periodic formation of alternating layers (channel layers, barrier layers, sacrificial layers) in a repeating sequence to build the three-dimensional stacked structure. This periodic layering approach allows for systematic manufacturing where the same deposition and etching cycles are repeated to create multiple memory cell layers, reducing process complexity compared to forming each layer individually with unique processes
Solution Approach 2:
The patent performs preliminary formation of the alternating channel-barrier-sacrificial layer stacks before forming the final memory layers. This preliminary structuring establishes the vertical architecture and material distribution in advance, simplifying subsequent processing steps. The sacrificial layers are pre-positioned to guide later etching and material deposition, reducing the complexity of forming the final memory device structure
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first sacrificial layer including a nitride over a first source layer, forming a second sacrificial layer including aluminum oxide over the first sacrificial layer, forming a second source layer over the second sacrificial layer, forming a stacked structure over the second source layer, forming a channel layer that passes through the stacked structure, the second source layer, the second sacrificial layer, and the first sacrificial layer, the channel layer being enclosed by a memory layer, forming a slit that passes through the stacked structure and the second source layer, forming a polysilicon spacer in the slit, forming an opening by removing the first sacrificial layer and the second sacrificial layer, exposing the channel layer by etching the memory layer, and forming a third source layer in the opening.