3D NAND Memory String Fabrication via Sacrificial Pattern Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional nonvolatile memory devices face challenges in manufacturing due to increased difficulties in the etch process and degraded operation characteristics as the stacked structure height increases, particularly when memory strings are arranged in a U shape, leading to insufficient cell currents and degraded operation characteristics during programming or erasing.
Innovation Solution
A method involving the formation of a sacrificial pattern, alternately stacked material layers, semiconductor patterns, and dielectric multi-layers, with a slit to expose the sacrificial pattern and form a spacer, followed by removing the sacrificial pattern to create openings and a connection pattern that directly contacts the semiconductor patterns, improving the structure and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the height of the stacked structure increases to improve integration density, then the degree of integration is improved, but the difficulty of the etch process increases
Solution Approach 1:
A sacrificial pattern is formed at the lower portion of the stacked structure before completing the stacking process. This preliminary structure serves as a support during subsequent etching operations, making it easier to etch through the tall stacked structure without collapsing or deforming the memory strings.
Solution Approach 2:
The sacrificial pattern acts as an intermediary support structure during the etching process. It provides mechanical support to the tall stacked structure during manufacturing, and is later removed to form the desired opening, thus mediating between the need for high integration and the difficulty of etching.
2Productivity
If memory strings are arranged in a U shape to improve integration, then the degree of integration is improved, but the channel length increases leading to decreased cell currents
Solution Approach 1:
Connection patterns are formed by extending in the first direction (horizontal dimension) to connect memory strings that are vertically stacked. This allows electrical connection without requiring the current to flow through a long U-shaped channel, thus maintaining adequate cell current while achieving high integration through vertical stacking.
3Productivity
If the channel length increases due to U-shaped memory string arrangement, then integration is improved, but operation characteristics are degraded due to insufficient currents
Solution Approach 1:
The connection path is segmented into two components: a vertical component through the stacked structure and a horizontal component through the connection pattern. This segmentation allows the current to flow through a shorter, more direct path by utilizing the vertical stacking dimension, thereby improving operation characteristics while maintaining high integration.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a sacrificial pattern, forming a first stacked structure including first material layers and second material layers alternately stacked on the sacrificial pattern, forming first semiconductor patterns passing through the first stacked structure and dielectric multi-layers surrounding the first semiconductor patterns, forming a slit passing through the first stacked structure and exposing the sacrificial pattern, forming a spacer on an inner wall of the slit, forming a first opening by removing the sacrificial pattern through the slit, forming a second opening by partially removing the dielectric multi-layers through the first opening to expose lower portions of the first semiconductor patterns, and forming a connection pattern in contact with the first semiconductor patterns in the first and second openings.