3D NAND Sealing Ring Structure for Edge Crack Containment
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Solution Overview
Problem
In the manufacturing process of semiconductor devices, particularly 3D NAND memory, die chipping occurs due to cracks extending into effective circuit areas, leading to yield loss and device failure.
Innovation Solution
A semiconductor device with a stacking structure comprising a memory array area and a sealing area, where at least two circles of dummy interconnection structures are formed around the memory array area, connected to a sealing ring body penetrating through the stacking structure, enhancing the sealing structure's protection and reducing the risk of edge cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple circles of dummy interconnection structures are added around the memory array area, then crack prevention capability is improved, but device complexity increases
Solution Approach 1:
The sealing structure is segmented into multiple functional components: sealing ring body, first dummy interconnection structures, and second dummy interconnection structures. Each component serves a specific purpose in crack prevention, with the segmentation allowing the structure to better distribute and resist crack propagation forces from different directions.
Solution Approach 2:
The sealing structure extends from a single-plane configuration to a multi-layer three-dimensional arrangement. The first dummy interconnection structures are positioned at a first height, while the second dummy interconnection structures are positioned at a second height different from the first height, creating vertical dimensionality that enhances crack prevention capability.
2Strength
If dummy interconnection structures are positioned at different heights, then crack resistance is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: first forming the sealing ring body and first dummy interconnection structures at a first height, then subsequently forming the second dummy interconnection structures at a second height. This segmentation allows each layer to be optimized and manufactured independently, reducing overall manufacturing complexity.
Solution Approach 2:
The sealing ring body and first dummy interconnection structures are formed in advance before the second dummy interconnection structures are added. This preliminary action establishes a stable base structure that guides subsequent manufacturing steps and ensures proper positioning of the multi-layer configuration.
Data Source
AI summary
Examples of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a memory system. The semiconductor device comprises: a stacking structure comprising a memory array area and a first sealing area; and at least one circle of sealing structure in the first sealing area and surrounding the memory array area, wherein the sealing structure comprises a sealing ring body penetrating through the stacking structure and at least two circles of first dummy interconnection structures connected with the sealing ring body.