3D NAND Memory Device With Segmented Bit Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining reliability due to increased channel resistance and decreased cell current, as well as limitations in chip area and bit cost, particularly in three-dimensionally stacked NAND-type flash memory configurations.
Innovation Solution
The semiconductor memory device employs a configuration with memory cell transistors stacked above a semiconductor substrate, featuring a specific arrangement of word line pillars, select gate lines, and contact plugs that allow for flexible channel length and increased cell density, while maintaining constant select gate contact region area, regardless of the number of layers stacked.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally stacked NAND-type flash memory configuration is used to increase storage capacity, then bit density is improved, but channel resistance increases and cell current decreases
Solution Approach 1:
The bit line is divided into multiple segments (first bit line, second bit line, third bit line, fourth bit line) that are selectively connected to different memory cell strings. This segmentation allows for reduced channel resistance by providing multiple parallel conduction paths while maintaining high bit density through the three-dimensional stacking configuration.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional stacked architecture by vertically stacking multiple semiconductor layers and memory cell strings. This dimensional change increases bit density by utilizing the vertical space above the substrate, while the segmented bit line configuration compensates for the increased channel resistance inherent in longer vertical channels.
2Quantity of substance
If three-dimensionally stacked NAND-type flash memory configuration is used to increase storage capacity, then bit density is improved, but chip area is constrained
Solution Approach 1:
The patent utilizes vertical stacking of multiple semiconductor layers (first, second, third, and fourth semiconductor layers) to increase storage capacity without proportionally increasing chip area. By stacking memory cell strings vertically and connecting them through selectively connected bit line segments, the design achieves high bit density within a constrained planar footprint.
Solution Approach 2:
Multiple memory cell strings (first, second, third, and fourth memory cell strings) are vertically stacked and electrically connected through shared bit line segments. This merging of multiple storage elements in the vertical dimension increases bit density while efficiently utilizing the available chip area without requiring proportional horizontal expansion.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.