3D NAND Memory Hole Structure With Segmented Charge Trap Layers
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Solution Overview
Problem
Current 3D NAND flash memory technologies face challenges in scaling memory cells vertically due to reduced inter-cell separation, which affects the retention performance of continuous charge trap layers.
Innovation Solution
A method for forming a memory structure with vertically separated lateral memory stacks, each comprising a discrete charge trap layer, achieved through an area-selective deposition process using sacrificial layers to define deposition-inhibiting areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If continuous charge trap layer is deposited along the sidewall of the memory hole, then the manufacturing process is simple, but the retention performance deteriorates at aggressive z-pitch scaling due to reduced inter-cell separation
Solution Approach 1:
The continuous charge trap layer is segmented into discrete charge trap layers for each memory cell by introducing sacrificial layers that define deposition-inhibiting areas. This segmentation prevents charge leakage between adjacent memory cells, thereby improving retention performance while maintaining a relatively simple manufacturing process through area-selective deposition
Solution Approach 2:
Sacrificial layers are introduced as intermediary elements that temporarily occupy space during deposition to define deposition-inhibiting areas. These sacrificial layers enable area-selective deposition of the charge trap material, ensuring discrete charge trap layers are formed only in desired locations, thus improving retention performance without significantly complicating the manufacturing process
2Productivity
If z-pitch scaling is performed to increase bit density, then the number of stacked memory cells increases, but the inter-cell separation reduces leading to poor retention performance
Solution Approach 1:
The charge trap layer is segmented into discrete portions for each memory cell using sacrificial layers as boundaries. This segmentation ensures that even at reduced z-pitch, each memory cell has its own isolated charge trap layer, preventing charge leakage to adjacent cells and maintaining retention performance while enabling higher bit density through increased stacking
Solution Approach 2:
Area-selective deposition is employed to provide different deposition qualities in different locations: deposition-inhibiting areas over sacrificial layers prevent charge trap material formation, while deposition-permitting areas on gate layers allow discrete charge trap layers to form. This local quality control ensures proper charge trap layer formation at aggressive z-pitch scaling
3Reliability
If discrete charge trap layers are formed by etching a continuous layer, then each memory cell gets separate charge trap layer, but the thickness control precision is reduced
Solution Approach 1:
Sacrificial layers are formed in advance to define deposition-inhibiting areas before the charge trap material deposition. This preliminary action establishes precise boundaries for where charge trap layers should form, allowing thickness to be controlled by deposition parameters rather than subsequent etching, thereby maintaining manufacturing precision while achieving proper charge trap layer separation
Solution Approach 2:
The mechanical etching process is replaced with a chemical deposition process controlled by area-selective properties. Instead of forming a continuous layer and mechanically removing portions through etching, the charge trap material is deposited only in desired locations through area-selective deposition, allowing precise thickness control through deposition time and parameters while naturally creating discrete layers for each memory cell
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable formation of interrupted charge trap layers at aggressive z-pitch scaling, improving retention performance and allowing precise control over charge trap layer thickness.
Implementation Method 1
forming a lateral memory stack in each second recessed area by selectively depositing, in the second recessed areas, a blocking oxide and, subsequently, a charge trap material, wherein the sacrificial layers define deposition-inhibiting areas for the selective deposition of the blocking oxide and the charge trap material
Implementation Method 2
after re-growing the inter-gate spacer layers, forming a tunneling oxide layer in the memory hole
Implementation Method 3
removing the sacrificial layers by etching from the memory hole
Implementation Method 4
forming second recessed areas in the sidewall by laterally etching back the gate layers relative the sacrificial layers from the memory hole
Implementation Method 5
forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the inter-gate spacer layers relative the gate layers from the memory hole
Data Source
Figure 1a~1b
Figure 2~3
Figure 4~5
AI summary
According to an aspect, there is provided a method for forming a memory structure (1) for a 3D NAND flash memory, the method comprising: forming a layer stack (10) over a substrate (2); forming first recessed areas (18) in a sidewall surrounding a memory hole (4) in the layer stack by laterally etching back inter-gate spacer layers (12) of the layer stack; forming sacrificial layers (20) in the first recessed areas (18); forming second recessed areas (22) in the sidewall by laterally etching back gate layers (14) of the layer stack; forming a lateral memory stack (27) in each second recessed area (22) by selectively depositing, in the second recessed areas, a blocking oxide (24) and, subsequently, a charge trap material (26); removing the sacrificial layers by etching from the memory hole; re-growing the inter-gate spacer layers such that the lateral memory stacks are vertically separated by the re-grown inter-gate spacer layers; forming a tunneling oxide layer (30) in the memory hole; and forming a channel layer (32) along the tunneling oxide layer.