3D NAND Memory Hole Formation via Segmented Etching
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Solution Overview
Problem
The challenge in manufacturing three-dimensional NAND flash memory is the difficulty in forming memory holes with high aspect ratios due to increased etching rates and potential stopping of etching processes, which hinders the increase in memory capacity and integration density.
Innovation Solution
The semiconductor memory device employs a stacked body with alternately stacked insulating and gate electrode layers, forming memory holes with a central insulating layer that allows for the formation of memory strings with high aspect ratios by dividing the central hole into upper and lower holes, facilitating continuous channel layer formation without deviation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory holes with high aspect ratios are formed to increase memory capacity, then memory capacity and integration density are improved, but etching rate reduction or process stoppage occurs
Solution Approach 1:
The patent divides the central hole into upper and lower holes that are formed at different depths. This segmentation allows the etching process to be performed in stages, preventing process stoppage and maintaining etching rate stability while achieving the high aspect ratio needed for increased memory capacity.
Solution Approach 2:
The patent forms a sacrificial layer and preliminary structures before forming the final memory holes. This preliminary action includes creating a template structure that guides the subsequent etching process, ensuring that the high aspect ratio holes can be formed without etching process failures.
2Quantity of substance
If the number of gate electrodes stacked in the stacked body is increased to increase capacity, then memory capacity is improved, but device complexity increases
Solution Approach 1:
The patent designs the stacked body structure with gate electrodes and insulating layers that serve multiple functions. The alternating stacking of insulating layers and gate electrode layers creates a multi-functional structure that provides both electrical isolation and control functions, allowing increased capacity without proportionally increasing complexity.
Solution Approach 2:
The patent implements a nested structure where memory holes are formed within the stacked body, and charge accumulation layers and semiconductor layers are nested within the memory holes. This nested arrangement allows multiple functional layers to be integrated in a compact manner, increasing capacity while managing structural complexity.
3Quantity of substance
If the size of the memory hole is scaled down to increase capacity, then memory capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a sacrificial layer and template structures as intermediary elements that facilitate the formation of small memory holes. These intermediary structures serve as guides and support during the etching process, enabling precise formation of scaled-down memory holes without excessive manufacturing precision requirements.
Solution Approach 2:
The patent employs parameter changes in the etching process, including adjusting etching conditions and using different etching rates for different stages. This allows precise control over memory hole dimensions at scaled sizes, achieving high capacity while managing manufacturing precision through process optimization.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a stacked body alternately stacking first insulating layers and gate electrode layers in a first direction; first to third semiconductor layers in the stacked body extending in the first direction; first to third charge accumulation layers; and a second insulating layer in the stacked body extending in the first direction, the second insulating layer contacting the first semiconductor layer or the first charge accumulation layer in a plane perpendicular to the first direction. A first distance between two end surfaces of the gate electrode layer monotonically increases in the first direction in a first cross section parallel to the first direction. A second distance between two end surfaces of the gate electrode layer monotonically increases in the first direction, decreases, and then monotonically increases in a second cross section parallel to the first direction different from the first cross section.