3D NAND Memory Structure With Segmented Storage Layers
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Solution Overview
Problem
Three-dimensional (3D) semiconductor devices face challenges with charge lateral migration due to shrinking device sizes, which affects the performance and reliability of 3D NAND memory devices, particularly in Flash memory devices, as the distance between word lines decreases, leading to increased charge migration issues.
Innovation Solution
The 3D memory device architecture includes interleaved conductive and dielectric layers with a memory film structure that separates the storage layer into isolated sections, preventing charge migration by isolating charge stored in each word line, and a method for forming this structure involves forming channel structures with dielectric and semiconductor layers, and separating the storage and tunneling layers to prevent charge leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is scaled down to increase storage density, then storage capacity is improved, but charge lateral migration increases causing performance degradation
Solution Approach 1:
The storage layer is segmented into multiple isolated sections along the channel length direction, with each section corresponding to a specific word line. Dielectric layers are inserted between adjacent storage layers to electrically isolate charges from different word lines, preventing lateral charge migration while maintaining high storage density in the scaled-down device structure
Solution Approach 2:
Different regions of the memory structure have different dielectric properties - the storage layer has high-k dielectric material for charge retention, while the inter-layer dielectric material has low-k properties to prevent charge migration. This local differentiation of dielectric quality enables simultaneous charge storage and isolation in the compact 3D structure
2Productivity
If word lines are placed closer together to increase vertical stacking density, then storage capacity is improved, but charge leakage between word lines increases
Solution Approach 1:
Low-k dielectric layers are introduced as intermediary materials between adjacent high-k storage layers. These intermediary dielectric layers act as barriers that prevent charge leakage between closely-spaced word lines, enabling high vertical stacking density without compromising electrical isolation between adjacent memory cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces charge migration, enhances the reliability of 3D memory devices, and maintains the strength of the memory structure, improving the performance and hot carrier resistance of 3D NAND memory devices.
Implementation Method 1
a tunneling layer over the semiconductor channel
Implementation Method 2
interleaved conductive and dielectric layers with a memory film structure that separates the storage layer into isolated sections
Data Source
AI summary
A three-dimensional (3D) memory device includes a first stack structure, a first channel structure, a second stack structure, and a second channel structure. The first stack structure includes interleaved first conductive layers and first dielectric layers. The first channel structure extends through the first stack structure along a first direction. The first channel structure includes a first semiconductor channel, and a first memory film over the first semiconductor channel. The first memory film includes a storage layer. The storage layer is separated by the first dielectric layers into a plurality of sections.