3D NAND Integrated Structure With Nested Select Gate Channels
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Solution Overview
Problem
Current NAND architecture for flash memory lacks improvements in structure and fabrication methods, which hinders the development of more efficient and reliable integrated flash memory systems.
Innovation Solution
The development of integrated structures with monolithic channel material adjacent to select devices and vertically-stacked memory cells, featuring alternating dielectric and conductive levels, and the use of conductive plugs to enhance the formation of NAND strings, allowing for improved select device gate material configurations and channel material extensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional NAND architecture is used, then manufacturing simplicity is maintained, but memory storage density and performance are limited
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertically-stacked three-dimensional architecture. Multiple memory cells are stacked along the vertical dimension, with alternating conductive and dielectric levels forming a tower structure. This dimensional change dramatically increases storage density within the same footprint area while managing complexity through systematic layering patterns.
Solution Approach 2:
The patent implements nested structures where select devices are integrated within the vertical stack of memory cells. The select device gate material is positioned at specific levels within the stacked architecture, with channel material extending through multiple levels. This nesting allows select devices to be embedded within the memory cell stack rather than placed separately, increasing density while organizing complexity hierarchically.
2Quantity of substance
If vertically-stacked memory cells are implemented, then storage density increases, but fabrication process complexity increases
Solution Approach 1:
The patent divides the memory structure into repeating modular units consisting of conductive levels, dielectric levels, and channel material segments. Each level can be deposited and patterned independently using sequential fabrication steps. This segmentation allows the complex vertical stack to be built incrementally through repeated application of standardized processing modules, making fabrication more manageable despite the increased vertical complexity.
Solution Approach 2:
The patent employs preliminary formation of sacrificial structures and templates before final memory cell creation. Conductive plugs and select device gate materials are positioned in advance at specific locations within the stack. Channel material is extended to predetermined lengths before final patterning. These preliminary actions establish the framework for subsequent steps, reducing overall fabrication complexity by pre-organizing the vertical architecture.
3Reliability
If select device gate material is extended vertically, then device control improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent creates equipotential regions by extending conductive material continuously through multiple vertical levels. Conductive plugs connect select device gate materials across different dielectric levels, establishing uniform electrical potential throughout the vertical stack. This equipotential design ensures consistent device control while reducing alignment precision requirements, as the continuous conductive paths are less sensitive to minor misalignments between deposited layers.
Data Source
AI summary
Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.