3D NAND Channel Thickening at Select Gates for Higher GIDL
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in enhancing gate-induced drain leakage (GIDL) for improved operational speed and efficiency, particularly in three-dimensional NAND strings with stacked-surrounding gate transistors, where existing structures do not effectively optimize semiconductor channel design for enhanced leakage and reduced erase voltage variations.
Innovation Solution
A semiconductor structure with a vertically extending memory opening and fill structure featuring a locally thickened semiconductor channel adjacent to select gate electrodes, formed through an alternating stack of insulating and sacrificial material layers, where the sacrificial layers are selectively etched and replaced with conductive layers to create a memory opening fill structure with specific lateral protrusions, enhancing GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor channels are made uniformly thick throughout the structure, then manufacturing simplicity is maintained, but GIDL enhancement is insufficient
Solution Approach 1:
The patent implements variable thickness semiconductor channels where the channel thickness is locally increased at specific positions (such as near select gate electrodes) to enhance GIDL effect. This is achieved by selectively removing sacrificial material at targeted locations before forming the channel, creating regions of different thickness within the same channel structure. The local quality principle resolves the contradiction by maintaining uniform manufacturing processes while achieving non-uniform channel thickness to improve GIDL without complicating the overall manufacturing approach.
2Reliability
If semiconductor channels are locally thickened to enhance GIDL, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by first forming sacrificial material layers at specific locations before forming the semiconductor channel. These sacrificial layers are strategically placed where channel thickening is desired (e.g., near select gates). The channel is then formed over the entire structure, and the sacrificial material is selectively removed to create the variable thickness profile. This preliminary placement of sacrificial material simplifies the overall process by enabling local thickening through a single channel formation step rather than requiring multiple complex fabrication steps.
Solution Approach 2:
The sacrificial material acts as an intermediary element that enables the creation of variable thickness channels. The sacrificial material is temporarily introduced, processed, and then removed to achieve the desired channel geometry. This intermediary approach allows complex channel structures to be formed using relatively simple processing steps, as the sacrificial material facilitates the creation of non-uniform thickness without requiring direct manipulation of the channel material itself.
3Reliability
If isotropic etch process is used to expand memory openings, then lateral protrusions are formed for GIDL enhancement, but etch selectivity requirements increase
Solution Approach 1:
The patent utilizes composite material structure with alternating layers of different materials (such as silicon nitride and silicon oxide) where each material has distinct etch characteristics. The isotropic etch process exploits the different etch rates and selectivities between these materials to selectively remove specific layers and create lateral protrusions in the channel. The composite structure enables the etch process to differentiate between regions, achieving the desired variable thickness profile through material composition rather than geometric complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases GIDL current, thereby accelerating erase operations and reducing erase voltage variations, leading to faster operational speeds in three-dimensional memory devices.
Implementation Method 1
expanding the memory opening at each level of the at least one sacrificial material layer by performing an isotropic etch process that etches the second sacrificial material at a higher etch rate than the first sacrificial material
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word line electrically conductive layers and a first select-level electrically conductive layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. A vertical cross-sectional profile of an outer sidewall of the vertical semiconductor channel is straight throughout the word line electrically conductive layers and contains a lateral protrusion at a level of the first select-level electrically conductive layer.