3D NAND Select Gate Transistor Self-Destruction for Data Security
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Solution Overview
Problem
Existing memory devices face challenges in permanently preventing access to memory cells, as typical erase operations are time-consuming and do not prevent further use or testing, and methods involving high voltages require additional components, which are undesirable for size and weight reduction.
Innovation Solution
Applying a strong erase bias to select gate transistors in NAND strings, which permanently increases their threshold voltages above the verify voltage, preventing programming or reading of memory cells through iterative erase-verify processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a typical erase operation is used to clear memory cells, then the memory cells are cleared, but the operation is time-consuming and does not prevent further use or testing
Solution Approach 1:
The patent changes the voltage parameter applied to select gate transistors from standard erase voltages to excessively high voltages (e.g., 20V or higher). This parameter change causes permanent threshold voltage shifts in the select gate transistors, making them non-functional for both data access and further testing, thereby achieving instant and permanent data security without time-consuming iterative operations
Solution Approach 2:
The patent applies the self-destruct mechanism to select gate transistors rather than directly to memory cells. By destroying the select gate transistors that control access to memory cells, the patent creates a copied effect where the entire memory block becomes inaccessible without physically damaging each individual memory cell, thus achieving rapid data security
2Reliability
If high voltages are applied to prevent access to memory cells, then access is prevented, but additional components are required, increasing size and weight
Solution Approach 1:
The patent utilizes the existing select gate transistors and voltage generation circuits already present in the 3D NAND memory device to apply self-destructive high voltages. The device's own internal structures are used to deliver the destructive voltage, eliminating the need for external high-voltage components or additional destruction circuits, thereby maintaining compact size and low weight while achieving permanent data security
Solution Approach 2:
The voltage generation circuits in the 3D NAND memory device are designed to serve multiple functions: normal operation voltages and self-destruct voltages. By programming the existing circuits to generate excessively high voltages, the patent makes the same hardware components perform both operational and destruction functions, eliminating the need for separate dedicated destruction components
3Productivity
If select gate transistors are disabled to prevent access, then memory access is blocked, but the method must be verified through iterative processes
Solution Approach 1:
The patent applies the self-destruct voltage in a single preliminary action to all select gate transistors simultaneously. This preliminary application of excessively high voltage permanently shifts the threshold voltages of all select gate transistors beyond recoverable limits, achieving instant data security without requiring multiple iterative verification steps or complex control sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively and irreversibly disables memory access, saving time and eliminating the need for additional components, while ensuring secure data protection and device integrity.
Implementation Method 1
Applying a strong erase bias to select gate transistors in NAND strings, which permanently increases their threshold voltages above the verify voltage
Data Source
AI summary
Apparatuses and techniques are described for performing an operation which irreversibly prevents access to a set of memory cells. The operation provides a strong erase bias for select gate transistors of NAND strings. The erase bias induces a phenomenon in the select gate transistors which permanently increases their threshold voltages. This prevents access to the memory cells such as for program or read operations. The operation can involve one or more erase-verify iterations. In each erase-verify iteration, an erase bias is applied to the select gate transistors such as by charging up the channels of the NAND strings and holding a control gate voltage of the select gate transistors at a relatively low level, thereby causing a relatively high channel-to-control gate voltage.