3D NAND Select Gate Separation via Non-Replacement Integration
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Solution Overview
Problem
Current 3D NAND devices face challenges in forming select-gate-for-drain (SGD) cuts, particularly when the number of holes between slits exceeds 8, as existing integration schemes block word line replacement and fail to meet the SGD-cut requirement, limiting the array size and cell density.
Innovation Solution
The implementation of a non-replacement gate integration scheme for forming SGD cuts without dummy holes, allowing for increased cell density by separating SGD transistors and enabling independent selection of holes under the same bit line using a combination of bit line and word line, and using a cluster tool for metal deposition and other processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of holes between slits is increased to reduce array size, then cell density is improved, but the need for additional SGD cuts increases device complexity and blocks word line replacement
Solution Approach 1:
The patent divides the memory stack into multiple regions separated by SGD cuts, with each region containing a manageable number of holes (e.g., 8 holes per region). This segmentation allows independent word line replacement in each region while maintaining high overall cell density through efficient use of vertical space and multiple bit line levels.
Solution Approach 2:
The patent utilizes the vertical dimension by implementing multiple bit line levels (e.g., 4 bit line levels) that can independently access holes at different vertical positions. This multi-level bit line architecture allows high cell density without requiring proportional increases in horizontal SGD cuts, as holes are accessed through their vertical positioning rather than horizontal separation.
2Adaptability or versatility
If SGD cuts are added to separate select gates for drains, then independent hole selection is enabled, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent performs preliminary patterning of the SGD cut regions before forming the actual cuts. Mask layers are deposited and patterned in advance to define the SGD cut locations, allowing subsequent etching processes to follow predetermined paths. This preliminary action simplifies the manufacturing process by establishing a clear roadmap for SGD cut formation rather than attempting to create them directly.
Solution Approach 2:
The patent introduces mask layers as intermediary structures that facilitate the formation of SGD cuts. These mask layers (e.g., nitride or oxide layers) serve as temporary structures that guide the etching process and protect surrounding regions. The mask layers are deposited conformally and then selectively removed to create the SGD cut patterns, making the complex cutting process more controllable and manufacturable.
3Quantity of substance
If traditional integration schemes are used, then existing process compatibility is maintained, but word line replacement is blocked and cell density cannot be increased
Solution Approach 1:
The patent implements a dynamic integration scheme where the SGD regions are designed to allow selective word line replacement. The mask layers and SGD cut structures are configured to be removable or modifiable in specific regions, enabling word lines to be replaced dynamically during manufacturing. This dynamic approach contrasts with traditional static integration schemes where all structures are fixed simultaneously.
Solution Approach 2:
The patent applies different structural characteristics to different regions of the memory device. SGD regions are designed with specific mask layer configurations that differ from regions requiring word line replacement. This local differentiation allows simultaneous optimization for both high cell density (through SGD cuts in some regions) and word line replacement capability (in other regions), rather than using a uniform structure throughout.
Data Source
AI summary
Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.