3D NAND Select Gate Voltage Control for Reliability
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face challenges in reliability due to misalignment and increased connection resistance between the memory cell array and the select gate transistor layer, leading to decreased cell current and operational efficiency.
Innovation Solution
The implementation of a nonvolatile semiconductor storage device with a memory cell array and a select gate transistor layer connected in series, where signals with different voltage levels are supplied to the select gate lines during read operations, and threshold voltages of drain side select transistors are individually controlled to improve ON resistance and reduce disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell array and select gate transistor layer are connected in series to increase capacity, then the storage capacity increases, but the connection resistance increases and reliability decreases
Solution Approach 1:
The select gate transistor layer is divided into multiple independent select gate transistors (first select gate transistor and second select gate transistor) connected in series. Each transistor can be independently controlled through separate select gate lines, allowing individual optimization of connection paths and reducing the cumulative effect of misalignment errors.
Solution Approach 2:
Different voltage levels are applied to different select gate lines (first select gate line and second select gate line) during read operations. The control circuit supplies signals with different voltage levels to each select gate line, allowing local optimization of electrical characteristics at different positions in the series connection, thereby reducing overall connection resistance.
2Quantity of substance
If multiple select gate transistors are connected in series to increase capacity, then the storage capacity increases, but the cell current decreases due to increased resistance
Solution Approach 1:
The control circuit supplies signals with different voltage levels to different select gate lines based on their specific positions and electrical characteristics in the series connection. This local optimization compensates for resistance variations and maintains adequate cell current flow through each transistor segment.
Solution Approach 2:
The voltage levels of select gate signals are dynamically adjusted during read operations. By changing the voltage parameters of control signals supplied to different select gate lines, the electrical characteristics of the series connection are optimized to maintain sufficient cell current while preserving increased storage capacity.
3Device complexity
If standard read operations are performed without differentiated voltage levels, then the device complexity is low, but read disturbances occur and reliability decreases
Solution Approach 1:
Different voltage levels are applied to different select gate lines during read operations to locally optimize the electrical characteristics of each transistor in the series connection. This reduces read disturbances by compensating for position-dependent resistance variations without requiring fundamental changes to the control circuit architecture.
Solution Approach 2:
The control circuit is configured to supply signals with different voltage levels to different select gate lines during read operations. This parameter differentiation allows the system to reduce read disturbances and improve reliability while maintaining relatively simple control logic that can be integrated into existing flash memory control architectures.
Data Source
AI summary
A nonvolatile semiconductor storage device includes a memory cell array layer that includes a plurality of nonvolatile memory cells connected in series in a vertical direction above a semiconductor substrate, a plurality of word lines respectively connected to gates of the plurality of nonvolatile memory cells, a select gate transistor layer that is located above the memory cell array and includes at least first and second select gate transistors connected in series in the vertical direction and to the plurality of nonvolatile memory cells, and at least first and second select gate lines respectively connected to the at least first and second select gate transistors, and a control circuit configured to execute a read operation on the nonvolatile memory cells, such that during a read period of the read operation, signals having different voltage levels are supplied to the at least first and second select gate lines.