3D NAND Select Gate Voltage Control for GIDL Management
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Solution Overview
Problem
In 3D non-volatile memory devices, controlling gate-induced drain leakage (GIDL) current is challenging due to unpredictable coupling ratios and select gate voltage differences, leading to excessive charging times and select gate degradation during erase operations in 3D NAND stacked memory structures.
Innovation Solution
The solution involves adjusting the select gate voltage dynamically during erase-verify iterations by stepping up the voltage based on the number of program-erase cycles, thereby maintaining a consistent drain-to-gate voltage difference across select gates, reducing degradation and improving control over GIDL generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the select gate voltage is kept fixed during erase operations, then the control circuit complexity is reduced, but the charging time of the floating body becomes excessive and select gate degradation increases
Solution Approach 1:
The select gate voltage is changed dynamically during erase operations. Specifically, the select gate voltage is increased to a higher level during the charge-up phase to accelerate floating body charging, then reduced to a lower level during the erase phase to prevent excessive GIDL current and select gate degradation. This dynamic voltage adjustment resolves the contradiction between charging speed and device reliability.
Solution Approach 2:
The erase operation is divided into periodic phases with different select gate voltage levels. The charge-up phase uses a higher voltage level, followed by the erase phase using a lower voltage level. This periodic voltage modulation allows the system to achieve both fast charging and controlled degradation, addressing the time-loss problem without requiring overly complex continuous control circuits.
2Speed
If the select gate voltage is increased to accelerate charging, then the charging speed improves, but the select gate degradation increases due to excessive GIDL current
Solution Approach 1:
The select gate voltage transitions dynamically between two distinct levels: a higher level during the charge-up phase to maximize charging speed, and a lower level during the erase phase to minimize GIDL current and protect the select gate. This temporal separation of voltage levels allows the system to achieve high charging speed without compromising select gate reliability.
Solution Approach 2:
The select gate voltage is preliminarily increased to a high level only for the necessary duration to charge up the floating body. Once charging is complete, the voltage is reduced to a lower level before significant degradation can occur. This preliminary high-voltage action achieves the charging goal while limiting subsequent harmful effects.
3Measurement precision
If the select gate voltage is adjusted dynamically during erase-verify iterations, then the control precision over GIDL current improves, but the control circuit complexity increases
Solution Approach 1:
The select gate voltage is adjusted dynamically between two discrete levels based on the operational phase (charge-up or erase). This dynamic adjustment provides precise control over GIDL current generation while maintaining relatively simple control circuitry, as the system only needs to switch between two predetermined voltage levels rather than continuously modulating the voltage.
Solution Approach 2:
The select gate voltage parameter is changed between two specific values depending on the operational phase. During charge-up, the voltage is set to a first level that generates sufficient GIDL current for rapid charging. During the erase phase, the voltage is changed to a second, lower level that limits GIDL current to prevent degradation. This parameter switching achieves precise control without requiring complex control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more predictable and efficient GIDL generation, reducing the time required to charge the floating body and minimizing select gate degradation, thereby enhancing the erase operation's reliability and efficiency in 3D NAND memory devices.
Implementation Method 1
controlling gate-induced drain leakage (GIDL) current is challenging due to unpredictable coupling ratios and select gate voltage differences, leading to excessive charging times
Data Source
AI summary
An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.