3D NAND Vector-Matrix Sensing With Common-Mode Current Cancellation

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Solution Overview

Problem

Existing 3D NAND-based vector-matrix multiplication circuits for neural networks face significant area requirements due to large capacitance areas in sensing circuits, which consume a substantial portion of the device's control circuitry.

Innovation Solution

Implement a reference current to reduce common mode current levels during sensing operations by discharging capacitors, thereby reducing the size requirements for capacitors in the sensing circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If large capacitance areas are used in sensing circuits to handle common mode current, then sensing accuracy is maintained, but the area occupied by control circuitry increases significantly

Engineering Contradiction:
Improvesensing accuracyVSAvoidcontrol circuitry area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent extracts the common mode current component from the sensing operation by using a reference current that matches the common mode signal. This allows the sensing circuit to focus only on the differential signal, enabling the use of smaller capacitors and reducing the overall control circuitry area while maintaining sensing accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter of capacitor size by introducing common mode current cancellation. This allows the capacitors to be discharged more efficiently and reduces their required capacitance value, thereby reducing the area occupied by the sensing circuit without compromising measurement precision.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If common mode current levels are high during sensing operations, then sufficient signal margin is maintained, but energy consumption and computational overhead increase

Engineering Contradiction:
Improvesignal marginVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent converts the harmful effect of high common mode current into a beneficial reference signal. By using the common mode current itself as a reference, the circuit can cancel it out in the differential sensing operation, reducing energy consumption while maintaining sufficient signal margin for reliable detection.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Area of stationary object

If capacitor size is reduced in sensing circuits, then area requirements are met, but the ability to handle common mode current is compromised

Engineering Contradiction:
Improvesensing circuit areaVSAvoidcommon mode current handling
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces a reference current as an intermediary that mediates between the small capacitors and the common mode current. This reference current acts as a buffer that allows small capacitors to effectively handle the common mode signal by providing a matching reference for cancellation, thus maintaining reliability while reducing area.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260073010A1Area efficient 3D NAND-based vector-matrix multiplier circuit with common-mode current cancellation
Publication Date: 2026.03.12 SANDISK TECHNOLOGIES LLC
  • US20260073010A1 patent drawing
  • US20260073010A1 patent drawing
  • US20260073010A1 patent drawing

AI summary

To reduce the area requirements for sensing circuits of 3D NAND-based vector-matrix multiplication circuitry where weight values for a neural network are stored differentially as current levels on pairs of memory cells, techniques are presented for reducing the common mode current levels during sensing operations. When discharging a first capacitor through a first of a memory cell of a pair of memory cells storing a weight value by a first bit line and discharging second capacitor through a second memory cell of the pair by a second bit line, a reference current is applied to the bit lines. The product of a weight value with an input vector values is then determined by comparing the voltage levels on the two capacitors. The use of the reference current reduces the amount of voltage swing in the two capacitors, reducing the size requirements for the capacitors.