3D NAND Source Side Select Transistor Threshold Voltage Control
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Solution Overview
Problem
In 3D stacked memory devices, achieving accurate threshold voltage for source side select transistors is challenging, leading to increased read disturb in memory cells near the source side select transistor if the threshold voltage deviates from the target value.
Innovation Solution
The method involves forming a source side select transistor with a semiconductor body in a memory hole within a stack of alternating dielectric and conductive layers, where sacrificial layers are removed to create recesses for precise doping, allowing for controlled threshold voltage through impurity introduction, thereby ensuring accurate operation of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for source side select transistor, then manufacturing process is simpler, but threshold voltage control precision is insufficient leading to read disturb
Solution Approach 1:
The fabrication process is segmented into distinct phases: forming sacrificial layers at specific positions, removing sacrificial layers to create recesses, and performing doping operations in the recesses. This segmentation allows precise control of threshold voltage by isolating the doping step to specific spatial and temporal windows, resolving the contradiction between precision and complexity.
Solution Approach 2:
Sacrificial layers are formed in advance at predetermined positions before the actual transistor fabrication. These preliminary sacrificial structures guide subsequent processing steps, ensuring that doping occurs at the correct locations with precise control over threshold voltage, while the complexity is managed through systematic pre-planning.
2Reliability
If threshold voltage is not accurately controlled, then manufacturing process is easier, but read disturb increases affecting memory operation accuracy
Solution Approach 1:
Sacrificial layers serve as intermediary structures that facilitate precise threshold voltage control. These temporary structures enable accurate positioning of doping regions without requiring complex direct patterning methods, thus improving reliability while maintaining relative ease of manufacture through the use of simple sacrificial material deposition and removal steps.
3Manufacturing precision
If doping is performed without recess formation, then fabrication steps are reduced, but doping precision and threshold voltage control are insufficient
Solution Approach 1:
Recesses are formed locally at specific positions where source side select transistors need doping. This local modification approach concentrates doping precision where needed without requiring global process changes, maintaining fabrication efficiency while achieving the necessary doping precision for accurate threshold voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the threshold voltage of the source side select transistor, reducing or preventing read disturb and enhancing the efficiency and accuracy of memory array operations.
Implementation Method 1
A dopant is introduced into the first horizontal recess by way of the vertical opening to dope the body of the source side select transistor
Data Source
AI summary
Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.