3D NAND Firmware Repair Using Shared CAM Address Mapping
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Solution Overview
Problem
The challenge of efficiently performing multi-plane read operations in 3D NAND memory devices without increasing manufacturing costs due to the need for multiple content addressable memories (CAMs) to repair firmware for defective memory cells or strings.
Innovation Solution
A content addressable memory (CAM) design with a set of registers, comparators, and multiplexers that facilitate multi-plane read operations by storing and comparing old addresses with input signals to generate new addresses for redundant memory elements, reducing the need for multiple CAMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple CAMs are used to support multi-plane read operations, then firmware repair capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements a single CAM structure that serves multiple memory planes through shared comparators and multiplexers. The CAM receives address inputs from multiple planes and routes them through shared comparison and selection logic, enabling one CAM to perform firmware repair for multiple planes simultaneously, thereby eliminating the need for separate CAMs per plane and reducing manufacturing cost.
Solution Approach 2:
The patent merges the firmware repair functionality for multiple memory planes into a single integrated CAM unit. By combining the address comparison and replacement logic into shared resources that serve all planes, the design achieves multi-plane support without replicating the entire CAM structure for each plane, thus reducing overall component count and manufacturing complexity.
2Ease of manufacture
If a single CAM is used for multi-plane read operations, then manufacturing cost is reduced, but address comparison speed may be degraded
Solution Approach 1:
The patent employs dynamic resource allocation through multiplexers that selectively route address inputs from different memory planes to the shared comparators. The system dynamically switches between planes based on operational requirements, allowing the single CAM to maintain high comparison speeds by processing one plane's address at a time without interference from other planes, thus preserving performance while reducing cost.
Solution Approach 2:
The patent implements periodic switching between different memory planes using the shared CAM resources. The multiplexers cycle through inputs from various planes in a controlled sequence, ensuring that each plane receives timely address comparison service while utilizing the same physical hardware, thereby maintaining overall system speed without requiring duplicate CAM structures.
Data Source
AI summary
The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.