3D NAND Memory Stacked Arrays with Shared Select Gates
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Solution Overview
Problem
As semiconductor memory devices shrink in size, there is a challenge in increasing memory density while maintaining efficient memory operations and reducing chip area usage, particularly in accessing and storing data across multiple levels of memory cell strings.
Innovation Solution
The implementation of stacked arrays with shared data detectors and hierarchical select gates allows for increased memory density by reducing peripheral circuitry and enabling efficient data access and storage across multiple levels of memory cell strings, with shared data detectors and inhibit voltage sources optimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory device dimensions are reduced to increase density, then chip area is reduced, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangements to three-dimensional vertically stacked memory cell strings. Multiple levels of memory cells are stacked above a common substrate, with select gates positioned at different vertical levels. This vertical stacking enables significant increase in storage density while maintaining manageable manufacturing dimensions and precision requirements, as the scaling occurs primarily in the vertical dimension rather than requiring proportional reduction in all lateral dimensions.
2Quantity of substance
If more memory cell strings are added to increase capacity, then memory density increases, but peripheral circuitry area and device complexity increase
Solution Approach 1:
The patent implements shared select gates that can be selectively activated to access different memory cell strings. The same select gate structure serves multiple functions by controlling access to different vertical levels and different string groups through selective voltage application. This multi-functional approach reduces the number of dedicated select gates needed, thereby reducing peripheral circuitry area and device complexity while maintaining the ability to access a large number of memory cell strings.
Solution Approach 2:
Multiple memory cell strings are merged into a three-dimensional stacked architecture where they share common substrate structures, select gates, and control circuitry. The patent combines multiple levels of memory cells into unified strings that can be accessed through shared control mechanisms, reducing the overall peripheral circuitry required compared to separate planar arrays.
3Quantity of substance
If three-dimensional stacked arrays are implemented to increase density, then memory capacity increases, but data access complexity and operation difficulty increase
Solution Approach 1:
The three-dimensional memory array is segmented into multiple independently controllable memory cell strings, each accessible through selective activation of specific select gates at different vertical levels. This segmentation allows the memory structure to be divided into manageable access units, where only the relevant segments need to be activated during read or write operations. The segmentation enables efficient data access by isolating operational activity to specific vertical levels and string groups, reducing interference and simplifying control logic despite the overall three-dimensional complexity.
Data Source
AI summary
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.