3D NAND Word Line Structure With Shared Contact Vias
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Solution Overview
Problem
The challenge in three-dimensional NAND flash memory devices is the difficulty in forming a large number of metal contact vias and interconnects in a reduced device space, which complicates the fabrication process and inefficiently utilizes space, as each word line requires a separate metal contact via and interconnect.
Innovation Solution
The solution involves conductively connecting word lines of the same tier together, allowing them to share a common metal contact via, reducing the number of vias and interconnects needed, and using a method that forms connection structures over the substrate to connect adjacent stack structures, simplifying the fabrication process and reducing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If each word line is connected to a separate metal contact via and interconnect, then each word line can be independently accessed, but the number of metal contact vias and interconnects increases significantly, complicating the fabrication process and reducing space utilization
Solution Approach 1:
Multiple word lines of the same tier are merged into a single conductive structure, allowing them to share common metal contact vias and interconnects. This reduces the total number of connections while maintaining the ability to independently select and access specific word lines through selective gating mechanisms.
Solution Approach 2:
The shared metal contact vias and interconnects serve multiple word lines simultaneously, making these connection structures multi-functional. A single via structure provides access to multiple word lines, reducing redundancy while preserving independent word line control capabilities.
2Difficulty of detecting and measuring
If each word line has a separate metal contact via, then word line identification and control is simplified, but the device size increases due to the large number of vias required in reduced device space
Solution Approach 1:
Multiple word line connection functions are merged into shared metal contact via structures. Instead of requiring separate vias for each word line, the invention combines access to multiple word lines through common via structures, significantly reducing the total area occupied by connection elements.
Solution Approach 2:
The invention transitions from a one-to-one mapping between word lines and contact vias to a many-to-one relationship, where multiple word lines share common vias. This dimensional change in the connection architecture reduces the spatial footprint of the interconnect structure.
3Ease of manufacture
If separate metal contact vias are formed for each word line, then fabrication can follow standard processes, but the fabrication process becomes more complex and time-consuming due to the large number of vias
Solution Approach 1:
The fabrication process merges the formation of multiple individual word line vias into a single shared via structure. This consolidation reduces the number of patterning, etching, and filling steps required, significantly decreasing fabrication time and process complexity while maintaining compatibility with standard semiconductor manufacturing processes.
Data Source
AI summary
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.