3D-NAND Memory Stack Using Silicon Germanium Layers
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Solution Overview
Problem
Existing 3D-NAND memory stacks with alternating layers of oxide and nitride face challenges in the memory hole etching process, resulting in tapering, bending, and bowing of memory holes, which complicates the realization of increased vertical stack height in 3D NAND devices.
Innovation Solution
A PECVD deposition method is employed to form a memory cell film stack with alternating layers of silicon and silicon germanium, involving surface treatment with plasma, formation of a wetting layer, and transitioning from a low to high deposition rate to create a uniform stack, which helps in forming a memory stack with improved etch process margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If alternating layers of oxide and nitride are used in the memory stack, then the vertical stack height can be increased, but the memory hole etching process becomes challenging resulting in tapering, bending, and bowing
Solution Approach 1:
The patent changes the material parameters of the memory stack by replacing traditional oxide-nitride alternating layers with a novel stack comprising a sacrificial layer, a first material layer (silicon), and a second material layer (silicon germanium). This parameter change in material composition fundamentally alters the etch selectivity and mechanical stress characteristics, enabling high aspect ratio memory hole etching without tapering, bending, or bowing while achieving increased vertical stack height
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element between the substrate and the alternating first and second material layers. This sacrificial layer serves as a temporary structural support during the memory hole etching process, enabling the formation of high aspect ratio holes without the harmful effects of tapering and deformation, and is subsequently removed to complete the memory hole formation
2Ease of manufacture
If replacement metal gate (RMG) process is used to build word lines, then the manufacturing process can be completed, but the memory hole etching process becomes more complex and problematic
Solution Approach 1:
The patent changes the material parameters of the memory stack to include silicon and silicon germanium layers with specific etch selectivity ratios, which simplifies the memory hole etching process when used in conjunction with RMG. The specific composition ratios and thickness parameters of these layers are optimized to provide adequate etch margins while maintaining compatibility with standard RMG processes for word line formation
3Length of stationary object
If high aspect ratio memory hole etch/fill processes are implemented, then the vertical stack height is achieved, but stress control becomes difficult
Solution Approach 1:
The patent utilizes the inherent stress characteristics of silicon germanium (second material layer) versus silicon (first material layer) by carefully controlling their thickness ratios and composition. This parameter optimization allows the alternating layer structure to self-compensate for stress during high aspect ratio memory hole etching, preventing bowing and maintaining structural integrity at increased vertical stack heights
Solution Approach 2:
The patent applies different material properties at different locations in the memory stack - silicon layers provide structural framework while silicon germanium layers provide stress management and etch selectivity. This local differentiation of material quality throughout the alternating layers enables simultaneous achievement of high aspect ratio etching and stress control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of a memory stack with more than 50 layers, addressing the difficulties in high aspect ratio memory hole etch/fill processes and stress control, thereby enhancing the vertical stack height of 3D-NAND devices.
Implementation Method 1
treating a surface of a substrate with a plasma, the plasma comprising one or more of ammonia (NH3), nitrogen (N2) or hydrogen (H2)
Implementation Method 2
A PECVD deposition method is employed to form a memory cell film stack with alternating layers of silicon and silicon germanium
Data Source
AI summary
Memory devices and methods of manufacturing memory devices are provided. A plasma enhanced chemical vapor deposition (PECVD) method to form a memory cell film stack having more than 50 layers as an alternative for 3D-NAND cells is described. The memory stack comprises alternating layers of a first material layer and a second material layer.