3D NAND Vector-Matrix Multiplier With Slave-Capacitor Accumulation
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Solution Overview
Problem
The limited throughput of 3D NAND-based vector-matrix multiplication circuits in deep learning systems hinders the overall speed of deep neural network accelerators, limiting their efficiency in computationally intensive tasks.
Innovation Solution
The circuit design includes reducing capacitance size by piling up charge on a slave capacitor not directly connected to the array and modifying operation phase timings, allowing faster execution of masking and scaling phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If charge is piled up on a slave capacitor not directly connected to the array, then the capacitance size is reduced and interconnect parasitics are reduced, but the circuit complexity increases
Solution Approach 1:
The slave capacitor is extracted from the direct array connection and placed in a separate location. This extraction reduces the capacitance size within the array and minimizes interconnect parasitics, thereby improving the vector-matrix multiplication speed while accepting increased circuit complexity as a trade-off
Solution Approach 2:
The slave capacitor acts as an intermediary element that stores charge separately from the main array. This mediator approach allows the circuit to maintain reduced capacitance and lower parasitics while still achieving the required computational function through additional control logic
2Productivity
If operation phase timings are modified to execute masking and scaling phases faster, then the throughput is improved, but the precision of timing control becomes more difficult
Solution Approach 1:
The operation is divided into periodic phases (masking phase, scaling phase, accumulation phase) with optimized durations. By making the timing periodic and structured, the circuit achieves higher throughput through faster phase execution while maintaining controllable precision through the regular rhythm of phase transitions
Solution Approach 2:
The timing parameters of different operation phases are changed and optimized independently. The masking and scaling phases are executed faster by adjusting their duration parameters, which improves overall throughput while the structured phase approach maintains sufficient timing control precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the speed of vector-matrix multiplication, improving the efficiency and speed of deep learning hardware by reducing interconnect parasitics and optimizing phase durations.
Implementation Method 1
reducing capacitance size by piling up charge on a slave capacitor not directly connected to the array
Data Source
AI summary
To improve the speed of the 3D NAND-based vector-matrix multiplication circuitry, the circuit is designed such that the charge is accumulated on a slave capacitor which is not directly connected to the array. The master capacitor is reset in each cycle, reducing the maximum swing on the bit lines and, hence, reduce the capacitance size. The reduction of the capacitance size will allow the vector-matrix multiplication to run much faster because of smaller interconnect parasitics. A second set of aspects is based on modification of timings of each operation phase. Rather than equal time slots dedicated to different operation phases (e.g., the integration and scaling), the circuit is modified such the masking and scaling phases would be executed much faster as they typically have a much faster time constant.