3D NAND Slit Formation via Dual Etching
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Solution Overview
Problem
The miniaturization of semiconductor storage devices with three-dimensional memory cell arrays is hindered by poor etching controllability of conductive layers, leading to tapered slits and increased depth, which results in wider upper openings and deeper slits, necessitating more dummy word lines and compromising the array's size.
Innovation Solution
The process of forming slits is divided into two etching processes: one for the stacked body using anisotropic etching and another for the columnar portions using wet etching, allowing for better control of slit depth and width, reducing the number of dummy word lines and achieving miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal material is used for the conductive layer and columnar portion, then electrical isolation is achieved, but etching controllability deteriorates
Solution Approach 1:
The patent divides the etching process into two separate stages: first etching the stacked body (insulating layer and conductive layer) to form an initial slit, then etching the columnar portion (semiconductor layer) to deepen and widen the slit. This segmentation allows optimization of etching conditions for each material type, achieving both good electrical isolation and precise dimensional control
Solution Approach 2:
The patent changes etching parameters between the two processes: using conditions optimized for anisotropic etching of the stacked body first, then switching to conditions suitable for isotropic etching of the columnar portion. This parameter change enables precise control of slit depth and width while maintaining etching quality for metal materials
2Reliability
If slit depth is increased to widen bottom portion, then electrical isolation is improved, but layout area increases
Solution Approach 1:
The patent segments the etching process to achieve progressive slit formation: the first process creates the initial slit structure with controlled depth, and the second process selectively deepens and widens it. This segmentation enables achieving sufficient electrical isolation without excessive overall slit dimensions that would increase layout area
Solution Approach 2:
The patent applies local quality by making the slit geometry non-uniform: the bottom portion is widened and deepened locally to ensure electrical isolation, while the upper portion maintains smaller dimensions. This localized modification achieves isolation requirements without proportionally increasing the entire slit's footprint
3Device complexity
If single etching process is used, then process complexity is reduced, but manufacturing precision deteriorates
Solution Approach 1:
The patent divides the etching operation into two distinct processes with different objectives and parameters: the first process targets the stacked body with specific depth and width controls, while the second process targets the columnar portion for deepening and widening. This segmentation, though increasing process steps, enables precise control of slit dimensions that a single process cannot achieve
Solution Approach 2:
The patent implements parameter changes between the two etching processes, adjusting etchant concentration, temperature, time, and other conditions to optimize for each specific etching target. This parameter optimization in each stage achieves superior manufacturing precision for slit depth and width control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over slit formation, reducing the layout area and number of dummy word lines, thereby facilitating the miniaturization of memory cell arrays while maintaining effective electrical isolation.
Implementation Method 1
The process of forming slits is divided into two etching processes: one for the stacked body using anisotropic etching
Implementation Method 2
another for the columnar portions using wet etching, allowing for better control of slit depth and width
Data Source
AI summary
A semiconductor storage device includes a substrate. A stacked body is disposed above the substrate and has an alternately stacked plurality of first insulating layers and plurality of conductive layers. A plurality of columnar portions penetrate the stacked body and include a core layer disposed at a center portion of the columnar portions, a semiconductor layer provided around the core layer, and a memory film disposed around the semiconductor layer. A slit divides an upper conductive layer at an upper portion of the stacked body. In a columnar portion overlapping the slit, the core layer or the memory film protrudes from the semiconductor layer.