3D NAND Gate Line Slit Etching to Eliminate Leakage Paths
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Solution Overview
Problem
Conventional 3D NAND memory devices face issues with residue metals causing leakage currents between adjacent memory cells due to incomplete removal of conductive material during the formation of gate line slits.
Innovation Solution
A method involving ion implantation to dope and weaken the conductive material on the sidewalls and bottom of the gate line slits, followed by an etch process to completely remove the conductive material, thereby preventing short circuits and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching process is used to form gate line slit, then manufacturing simplicity is maintained, but conductive material residue remains causing leakage currents
Solution Approach 1:
The patent applies preliminary action by performing ion implantation doping on the conductive material layer before the etching process. This pre-treatment weakens the conductive material at the gate line slit location, ensuring complete removal during subsequent etching and eliminating residue that causes leakage currents.
Solution Approach 2:
The patent changes the physical-chemical parameters of the conductive material through ion implantation doping. The doping process modifies the material properties, making the conductive material more susceptible to etching removal while maintaining electrical functionality in retained areas.
2Reliability
If ion implantation and etch process are added to remove conductive material residue, then leakage currents are eliminated, but manufacturing complexity increases
Solution Approach 1:
The ion implantation doping is performed as a preliminary step before etching to selectively weaken the conductive material at critical locations. This ensures complete removal of residue during etching while maintaining a systematic and controllable manufacturing process.
Solution Approach 2:
The ion implantation process acts as an intermediary step that modifies the conductive material properties, creating a gradient of susceptibility to etching. This mediator process enables selective removal of conductive material residue without affecting other structures.
3Reliability
If conductive material layer is completely removed from gate line slit, then leakage paths are blocked, but additional processing steps are required
Solution Approach 1:
The conductive material is pre-weakened through ion implantation doping before the etching process. This preliminary action ensures that the subsequent etching step can completely remove the conductive material from the gate line slit in a single pass, improving fabrication efficiency.
Solution Approach 2:
By changing the physical-chemical parameters of the conductive material through doping, the etching process becomes more effective and selective. This parameter change allows for complete removal of conductive material residue, blocking leakage paths between adjacent memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively eliminates residue conductive material, ensuring no leakage currents occur between adjacent memory cells, enhancing the reliability and performance of the 3D NAND memory device.
Implementation Method 1
performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit
Implementation Method 2
performing an etch process to remove the conductive material layer that is weakened by the ion implantation process from the sidewall and the bottom of the gate line slit
Data Source
AI summary
Three-dimensional NAND memory device and method that eliminate leakage currents and short circuits are provided. The method includes: forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, where the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit; and performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process.