3D NAND Word Line Contact Structure With Slit Gouging Control
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Solution Overview
Problem
The challenge of forming accurate word line contacts in 3D NAND memory devices becomes increasingly difficult as the number of word line layers increases, necessitating additional processes like TS (topside nitride) SiN and NDC (carbon doped nitride) deposition, which complicates the manufacturing process and increases costs.
Innovation Solution
A new architecture is introduced that simplifies the formation of stair step contacts (SCTs) by applying sequential processes including oxide deposition, etching, tungsten deposition, and oxide filling, with a tungsten plug formation to create word line contacts, and incorporates a trench structure under the gate line slit to control the position of the slit gouging, using a tungsten plate stop layer to prevent backside dummy channel structure punching through the stair step area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word line layers is increased to achieve greater storage capacity, then the storage capacity is improved, but the difficulty of forming accurate word line contacts increases and manufacturing complexity increases
Solution Approach 1:
A trench structure is formed extending from the first surface through the gate line slit structure to a depth that exposes the second dielectric structure before word line contact formation. This preliminary trench formation establishes precise spatial relationships and provides physical guides for subsequent contact alignment, enabling accurate word line contact placement even as the number of word line layers increases to achieve greater storage capacity.
Solution Approach 2:
The trench structure serves as an intermediary element that mediates between the gate line slit structure and the word line layers. The trench provides a physical framework that guides contact formation and ensures proper alignment with underlying word line layers, simplifying the manufacturing process while maintaining accuracy as device complexity increases.
2Manufacturing precision
If additional processes like TS SiN and NDC deposition are applied to form accurate word line contacts, then the manufacturing precision is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The trench structure is formed in advance with specific dimensions and positioning that pre-establish the spatial framework for word line contact formation. This preliminary action defines the contact location and orientation, eliminating the need for additional TS SiN and NDC deposition processes while maintaining manufacturing precision.
Solution Approach 2:
The complex multi-step deposition process (TS SiN, NDC) is extracted and replaced by the simpler trench-based geometric constraint approach. The trench structure provides the necessary alignment guidance without requiring the additional material deposition steps, thereby reducing device complexity while preserving word line contact placement accuracy.
3Manufacturing precision
If the trench structure is formed to control slit gouging position, then the manufacturing precision is improved, but the manufacturing process complexity increases
Solution Approach 1:
The trench formation process is merged with the existing gate line slit structure formation process. The trench is formed as an integrated feature that simultaneously defines the slit opening position and provides the framework for subsequent word line contact formation, achieving precise position control without adding separate manufacturing steps.
Solution Approach 2:
The trench structure serves multiple functions: it controls the gate line slit opening position, provides alignment guidance for word line contact formation, and establishes the spatial relationship between different device layers. This multi-functionality achieves manufacturing precision without proportionally increasing process complexity.
Data Source
AI summary
A semiconductor device semiconductor device includes a stack having a first surface and a second surface opposing the first surface. The stack can include word line layers and insulating layers alternating with the word line layers between the first surface and the second surface. The stack can further include a process stop layer between the lower most insulating layer and the second surface. The stack can extend along an X-Y plane having an X direction and a Y direction perpendicular. The semiconductor device can further include a slit structure crossing the stack between the first surface and the second surface in Z direction. In a cross-section perpendicular to the Y direction, distances between the slit structure and the process stop layer at two sides of the slit structure are each larger than distances at either side of the slit structure between the word line layers and the slit structure.