3D NAND Source Structure With Slit Support for Block Integrity

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Solution Overview

Problem

Planar NAND flash memory devices have reached storage limits, and 3D NAND memory devices face challenges in maintaining memory block integrity due to deformation of gate line slits during fabrication, leading to electrical leakage and misalignment issues.

Innovation Solution

The implementation of 3D memory devices with source structures featuring support structures that divide slit openings into source contacts, reducing resistance by conductively connecting adjacent source contacts through a connection layer, eliminating the need for contact plugs and enhancing structural stability during fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If gate line slits are formed during fabrication, then source contacts can be created, but deformation occurs leading to electrical leakage and misalignment

Engineering Contradiction:

Improvesource contact alignmentVSAvoidmemory block integrity

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The support structure is formed beforehand to divide the gate line slit into multiple sections before the slit opening formation process. This preliminary structural division prevents deformation during subsequent fabrication steps, maintaining both alignment precision and memory block integrity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The support structure acts as an intermediary element between the gate line slit and the source contacts. It provides mechanical support and structural stability during the fabrication process, preventing deformation that would otherwise cause misalignment and electrical leakage.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If traditional source structures are used, then fabrication can proceed, but resistance is high requiring additional contact plugs

Engineering Contradiction:

Improvecontact structureVSAvoidsource structure resistance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The connection layer merges multiple source contacts into a unified conductive structure, eliminating the need for separate contact plugs. This integration reduces the overall device complexity while maintaining low resistance through the continuous conductive path provided by the connection layer.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The invention extracts and eliminates the need for contact plugs by using the connection layer to directly connect source contacts to the control gate. This removal of unnecessary components simplifies the device structure and reduces resistance.

Inventive Principle:

Principle #2Taking out (Extraction)

3Quantity of substance

If planar memory cells are scaled to smaller sizes, then storage density increases, but process technology becomes challenging and costly

Engineering Contradiction:

Improvememory densityVSAvoidfabrication process

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The invention transitions from planar to three-dimensional architecture by forming vertical memory blocks stacked above the substrate. This dimensional change allows continued scaling and increased memory density while using fabrication processes that are more manageable and less costly than further planar scaling.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces source structure resistance, minimizes deformation, and maintains memory block integrity, thereby improving the reliability and efficiency of 3D NAND memory devices.

Implementation Method 1

two adjacent ones of the plurality of source contacts are conductively connected to one another by a connection layer

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS11785772B2Three-dimensional memory device with source structure and methods for forming the same

Publication Date: 2023.10.10 YANGTZE MEMORY TECH CO LTD

AI summary

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers, a plurality of channel structures extending in the memory stack, and a source structure extending in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. Two adjacent source contacts are conductively connected to one another by a connection layer, the connection layer includes a pair of first portions being over the two adjacent ones of the plurality of source contacts and a second portion between the pair of first portions. A support structure is between the two adjacent source contacts. The support structure includes a cut structure over interleaved a plurality of conductor portions and a plurality of insulating portions.