3D NAND Programming Voltage Control Using Smart Verify and Bitscan
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Solution Overview
Problem
Existing memory cell programming techniques face challenges in setting an optimal initial programming voltage, leading to overprogramming or reduced programming performance due to variations across memory blocks and word lines, which can result in increased error rates and inefficiencies.
Innovation Solution
Implementing a smart verify operation to acquire an initial programming voltage, followed by a bitscan operation to adjust the voltage based on the highest verified state, ensuring accurate and efficient programming across subsequent wordlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the initial programming voltage is set high to improve programming performance, then programming speed increases, but overprogramming of memory cells occurs
Solution Approach 1:
The patent performs a smart verify operation before actual programming to determine the optimal initial programming voltage for each memory block. This preliminary measurement allows the system to acquire threshold voltage information and calculate an appropriate starting voltage that prevents overprogramming while maintaining good programming performance.
Solution Approach 2:
The patent dynamically adjusts the initial programming voltage parameter based on the results of the smart verify operation. By changing the voltage parameter according to the specific characteristics of each memory block (threshold voltage distribution, process variations), the system optimizes programming performance for each block while avoiding overprogramming issues.
2Reliability
If the initial programming voltage is set low to avoid overprogramming, then programming reliability improves, but programming performance deteriorates
Solution Approach 1:
The system performs a smart verify operation as a preliminary step to measure the actual threshold voltages of memory cells in each block. This allows the system to determine the minimum sufficient programming voltage needed, ensuring both accuracy and performance rather than using a fixed low voltage that would harm performance.
Solution Approach 2:
The patent calculates and applies an optimized initial programming voltage parameter for each memory block based on the smart verify results. This dynamic parameter adjustment ensures that each block receives the appropriate voltage level - high enough for good performance but not so high as to cause overprogramming, thereby resolving the contradiction between reliability and productivity.
3Reliability
If smart verify operation is performed frequently to maintain accurate programming voltages, then programming reliability improves, but time consumption increases
Solution Approach 1:
The smart verify operation is performed as a one-time preliminary action before programming begins, rather than continuously during programming. This preliminary measurement captures the threshold voltage characteristics once, and the resulting optimized voltage parameters are then used for all subsequent programming operations in that memory block, significantly reducing time consumption while maintaining voltage accuracy.
Solution Approach 2:
The system uses the smart verify operation to self-determine the optimal programming parameters for each memory block. By having the memory block itself provide information about its characteristics through the verify operation, the system eliminates the need for external calibration or continuous monitoring, reducing time overhead while ensuring accurate programming voltages.
Data Source
AI summary
A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.