3D NAND Source Stack Dielectric Layout to Prevent Field Shielding
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Solution Overview
Problem
Conventional 3D NAND electronic devices face challenges in designing and fabricating due to etching complexities through multiple polysilicon materials, leading to shielding of the electric field and difficulty in turning on memory cell channels during read operations.
Innovation Solution
Incorporating a doped dielectric material or high-k dielectric material between the source contact and tiers, which provides a controlled distance and reduces electrical field termination, allowing for improved channel conductance and reduced charge trap interactions by eliminating polysilicon shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped polysilicon material is used for lateral contact with channels, then electrical connection is achieved, but etching through multiple polysilicon materials causes processing challenges and shielding of electric field
Solution Approach 1:
The patent introduces a dielectric material layer as an intermediary between the polysilicon channel and the polysilicon contact. This dielectric layer prevents direct etching interaction between the channel and contact polysilicon, eliminating the shielding effect and simplifying the etching process while maintaining electrical connection through the dielectric material.
Solution Approach 2:
The patent extracts the problematic polysilicon material from the contact region and replaces it with a dielectric material. This removal of polysilicon from the contact area eliminates the etching complexity and electric field shielding issues, while the dielectric material provides the necessary electrical isolation and connection functionality.
2Reliability
If polysilicon material is used for lateral contact, then channel connection is achieved, but electric field shielding occurs making channel difficult to turn on
Solution Approach 1:
The dielectric material serves as an intermediary that allows electric field penetration while maintaining electrical isolation. It mediates between the channel and contact regions, enabling the channel to be turned on without the harmful shielding effect that occurs with direct polysilicon contact.
Solution Approach 2:
The patent changes the material parameter from conductive polysilicon to insulating dielectric material in the contact region. This parameter change transforms the harmful electric field shielding into beneficial electric field transmission, allowing proper channel activation while maintaining electrical isolation.
3Device complexity
If multiple polysilicon materials are stacked, then device structure is formed, but total thickness increases causing etching challenges
Solution Approach 1:
The dielectric material acts as an intermediary layer that separates and isolates the polysilicon structures. This intermediary layer prevents the etching process from interacting with multiple polysilicon materials simultaneously, reducing the total effective thickness that needs to be etched through while maintaining the multi-layer device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances electron flow control and reduces charge traps, improving the electrical performance and fabrication margin of 3D NAND memory devices by separating the source contact from the select gate source, thus overcoming the limitations of conventional polysilicon materials.
Implementation Method 1
controlling a distance between the source contact and select gate source of the tiers, reducing electrical field termination
Implementation Method 2
reduces charge trapping, enhancing electrical performance by separating the source contact from the tiers and minimizing electrical interactions
Data Source
AI summary
Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.