3D NAND Source Structure With Three Source Layers for Yield Stability
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining high electrical properties and production yield due to increased integration, which can lead to reduced reliability and performance.
Innovation Solution
A semiconductor device is designed with a source structure comprising three source layers, a gate stack structure with alternately stacked dielectric and conductive patterns, and a memory channel structure that includes a channel layer, a tunnel dielectric layer, a data storage layer, and a blocking layer. The third source layer directly contacts the data storage layer, enhancing the electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of source layers is increased to three layers, then the electrical properties and reliability are improved, but the device complexity increases
Solution Approach 1:
The source structure is divided into three distinct source layers (first source layer, second source layer, third source layer) stacked vertically. Each layer serves specific functional purposes: the first source layer contacts the channel layer, the second source layer contacts the data storage layer, and the third source layer contacts the blocking layer. This segmentation allows independent optimization of electrical properties at different interfaces, improving overall device reliability while maintaining manageable complexity through modular design.
2Productivity
If the source layers are increased to enhance electrical properties, then the production yield improves, but the manufacturing precision requirements increase
Solution Approach 1:
The invention transitions from a planar source structure to a vertical three-dimensional stacked architecture. By stacking source layers in the vertical dimension rather than expanding horizontally, the device achieves improved electrical properties and higher production yield without proportionally increasing lateral manufacturing precision requirements. The vertical stacking allows standard fabrication processes to maintain acceptable alignment tolerances while achieving the desired performance enhancement.
Data Source
AI summary
A semiconductor device includes a source structure having a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer. A gate stack structure is on the source structure. The gate stack structure includes dielectric patterns and conductive patterns that are alternately stacked. A memory channel structure penetrates the gate stack structure. The memory channel structure includes a channel layer. A data storage layer surrounds the channel layer. A blocking layer surrounds the data storage layer. The second source layer includes an inner sidewall directly contacting the channel layer. The third source layer includes an inner sidewall directly contacting the data storage layer.