3D NAND Source Connection Layout for Capacity and Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity while maintaining electrical characteristics and reliability.
Innovation Solution
A semiconductor device design featuring a first and second semiconductor structure with stacked gate electrodes, channel structures, and a unique source connection pattern that overlaps and extends horizontally, providing improved electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but electrical characteristics and reliability may deteriorate
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers (first and second semiconductor structures stacked along vertical direction). This dimensional change increases storage capacity while maintaining electrical performance through careful design of vertical interconnections and bonding structures.
Solution Approach 2:
The patent implements nested structures where gate electrodes are stacked within channel structures, and multiple semiconductor structures are stacked together with bonding structures connecting them. The source connection pattern is nested within the second substrate, with via patterns extending through the substrate to connect source regions. This nesting approach maximizes storage density while maintaining reliable electrical connections.
2Quantity of substance
If complex stacked structures with multiple layers are implemented, then data storage capacity increases, but device complexity increases
Solution Approach 1:
The patent divides the memory device into distinct segmented structures: first and second semiconductor structures stacked separately, each with their own substrates, circuit devices, and interconnection structures. The gate electrodes are segmented into multiple layers (first gate electrode, second gate electrode, etc.) stacked vertically. This segmentation allows for modular manufacturing and simplifies the fabrication process despite the three-dimensional complexity.
Solution Approach 2:
The bonding structures serve multiple functions: they mechanically connect the first and second semiconductor structures, provide electrical interconnection between layers, and maintain structural alignment. The source connection pattern simultaneously provides electrical connection to source regions, defines active areas, and serves as a structural element within the stacked architecture. This multi-functionality reduces the number of separate components needed.
Data Source
AI summary
A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.