3D NAND Source Line Layout for High-Layer Memory Stacks
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Solution Overview
Problem
The challenge in forming 3D NAND memory devices is that as the number of layers increases, it becomes harder to form a source line underneath, leading to low yield and manufacturing complexity.
Innovation Solution
The solution involves forming a source line using a top surface process in a 3D NAND memory device, which simplifies the formation process and improves yield. Additionally, the 3D NAND can be formed in a high thermal budget process without affecting a CMOS wafer, allowing for enhanced semiconductor device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in 3D NAND memory increases to improve storage capacity, then storage density is improved, but the difficulty of forming the source line underneath increases and manufacturing yield decreases
Solution Approach 1:
The source line is formed above the memory array instead of underneath, completely inverting the conventional source line placement. This allows the source line to be formed after the memory stack is built, avoiding the difficulty of forming it underneath high-layer structures and enabling simpler manufacturing processes.
Solution Approach 2:
The source line is extended in the horizontal direction above the memory array rather than being confined to a planar configuration underneath. This dimensional change allows the source line to access multiple memory strings from above, simplifying the formation process while maintaining electrical connectivity.
2Quantity of substance
If the number of layers in 3D NAND memory increases to improve storage capacity, then storage density is improved, but manufacturing complexity increases
Solution Approach 1:
By inverting the source line placement from underneath to above the memory array, the manufacturing process is simplified. The source line can be formed using standard deposition and patterning processes after the memory stack is complete, avoiding complex alignment and formation steps that would be required underneath high-layer structures.
Solution Approach 2:
The memory stack is formed first as a preliminary structure, and then the source line is added in a subsequent step. This preliminary action allows the complex memory stack to be built using optimized processes, followed by a simpler source line formation process that does not interfere with the already-formed stack.
3Reliability
If high thermal budget process is used to form 3D NAND memory, then semiconductor device performance is improved, but CMOS wafer is affected and performance deteriorates
Solution Approach 1:
The fabrication process is segmented into separate stages: the 3D NAND memory is formed on one wafer using high thermal budget processes, then the completed memory array with source line is bonded to a separate CMOS wafer. This segmentation allows each component to be optimized independently, with the memory benefiting from high-temperature processing and the CMOS remaining protected from thermal damage.
Solution Approach 2:
A carrier wafer serves as an intermediary substrate during the fabrication process. The 3D NAND memory is built on the carrier wafer using high thermal budget processes, then the memory array is transferred to the final CMOS substrate through bonding. The carrier wafer acts as a mediator that protects the CMOS from direct exposure to damaging high-temperature processes.
Data Source
AI summary
An integrated circuit structure includes a substrate, an interconnect stack, a first memory array, and a source line. The interconnect stack is over the substrate. The first memory array is over the interconnect stack and includes memory elements stacked in a vertical direction each comprising a conductive layer. The first memory array further includes a memory layer electrically connecting to the conductive layers of the memory elements and extending downwardly from a topmost one of the conductive layers to a lowermost one of the conductive layers; and a channel layer extending along a sidewall of the memory layer. The source line is in contact with a top end of the channel layer and laterally extends across the first memory array.