3D NAND Source Line Segmentation for Wafer Warpage Control
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Solution Overview
Problem
Memory devices with three-dimensionally arranged memory cells face warpage issues due to stress in metal source lines, which can lead to manufacturing challenges and reduced chip reliability.
Innovation Solution
Incorporating stress relaxation portions, such as recesses or through-holes, in the conductive layer of the source line below the semiconductor pillar, made from low-resistance metal materials like tungsten, to reduce thermal expansion-induced stress and enhance wafer stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source line is made from low-resistance metal material to distribute electric potential uniformly, then electrical conductivity is improved, but wafer warpage occurs due to stress in the metal material
Solution Approach 1:
The conductive layer is divided into multiple segments separated by insulating layers, creating a multi-layer structure. This segmentation allows each conductive layer to be thinner and less stressful, while collectively providing the needed electrical conductivity through parallel conduction paths.
Solution Approach 2:
The source line structure uses a composite of conductive layers and insulating layers, combining materials with different properties. The conductive layers provide electrical conductivity while the insulating layers provide mechanical support and stress relief, creating a composite structure that balances both requirements.
2Reliability
If the source line is made from metal material to reduce contact resistance, then electrical connection is improved, but thermal expansion-induced stress increases causing wafer warpage
Solution Approach 1:
By segmenting the conductive layer into multiple thinner layers separated by insulating layers, the total metal volume is reduced, thereby reducing thermal expansion stress while maintaining electrical conductivity through the parallel layer structure.
Solution Approach 2:
The insulating layers act as intermediaries between the conductive layers, providing mechanical decoupling that reduces stress transmission. These intermediary layers allow thermal expansion to occur independently in each conductive layer without compounding stress effects.
3Reliability
If a plate-like source line is used to connect semiconductor channels, then electrical connection is achieved, but manufacturing precision is reduced due to wafer warpage
Solution Approach 1:
The plate-like source line is segmented into multiple thinner conductive layers separated by insulating layers. This multi-layer structure reduces warpage while maintaining electrical connection, thereby improving manufacturing precision without sacrificing electrical connectivity.
Solution Approach 2:
The source line is transformed from a simple metal plate to a composite multi-layer structure with alternating conductive and insulating layers. This composite structure provides both electrical connectivity and mechanical stability, enabling higher manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes wafer warpage and reduces contact resistance by increasing the contact area between the conductive and semiconductor layers, thereby improving the overall performance and reliability of the memory device.
Implementation Method 1
to reduce thermal expansion-induced stress and enhance wafer stability
Implementation Method 2
reduces contact resistance by increasing the contact area between the conductive and semiconductor layers
Data Source
AI summary
According to an embodiment, a memory device comprises a conductive layer containing a metal, a semiconductor layer on the conductive layer, electrode layers stacked on the semiconductor layer in a stacking direction, a semiconductor pillar penetrating the electrode layers in the stacking direction and electrically connected to the semiconductor layer, and a charge trap layer between the electrode layers and the semiconductor pillar. The conductive layer has a recess or a through-hole below the semiconductor pillar.