3D NAND Source Structure Patterning After Logic Wafer Bonding
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Solution Overview
Problem
Conventional microelectronic devices face challenges in reducing feature dimensions and separation distances while maintaining performance and simplifying fabrication, particularly due to processing conditions affecting control logic devices in memory devices like 3D NAND Flash memory.
Innovation Solution
A method involving the formation of a microelectronic device structure with a base structure, doped semiconductive material, and a stack structure with alternating conductive and insulative layers, where cell pillar structures extend through the stack and base, followed by attaching a control logic device structure and patterning the semiconductive material to form source structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature dimensions and separation distances are reduced to increase integration density, then device density increases, but processing conditions deteriorate and control logic device performance is affected
Solution Approach 1:
The device is divided into separate regions: a memory array region with vertically stacked memory cells and a control logic region with control logic devices. This segmentation allows each region to be optimized independently - the memory array can achieve high density through vertical stacking while the control logic region maintains larger feature dimensions and separation distances for reliable processing
Solution Approach 2:
The memory array transitions from planar two-dimensional arrangement to three-dimensional vertical stacking, increasing device density by utilizing the vertical dimension. Memory strings extend vertically through multiple decks with tiers of conductive structures, allowing more memory cells to be packed into a smaller footprint without compromising control logic performance
2Quantity of substance
If vertical memory array architectures are used to increase memory density, then memory capacity increases, but fabrication complexity increases due to processing conditions
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the memory array structure with vertical stacks, then separately forming the control logic region. This allows complex vertical memory structures to be created first, followed by addition of control logic, simplifying the overall fabrication sequence compared to integrating both simultaneously
Solution Approach 2:
The memory array structure including vertical memory strings, decks, and conductive structures is formed preliminarily before adding control logic devices. This preliminary formation of the complex vertical structure enables subsequent control logic integration without requiring rework of the memory array, reducing overall fabrication complexity
3Adaptability or versatility
If control logic devices are integrated with memory array, then device functionality improves, but manufacturing cost increases
Solution Approach 1:
The device is segmented into memory array region and control logic region that can be formed in separate fabrication sequences and then integrated. This segmentation allows standardization of each region's fabrication process, reducing manufacturing complexity and cost while maintaining full device functionality with both memory storage and control operations
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.