3D NAND Source Formation via Sacrificial Pillar Removal
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Solution Overview
Problem
The increasing aspect ratios of memory cell pillars in semiconductor devices lead to alignment issues during the pillar punch etch process, making it challenging to electrically connect channel regions to the source in vertical memory arrays, particularly in high-density 3D NAND Flash memory devices.
Innovation Solution
A semiconductor device design where the source is positioned below the memory cells and surrounded by cell films, eliminating the need for a pillar punch etch process by forming sacrificial structures and support pillars to enable electrical contact, allowing for uniform doping and reliable connection without alignment complications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of memory cell pillars is increased to achieve higher memory density, then the number of memory cells per die area increases, but alignment issues during pillar punch etch process worsen
Solution Approach 1:
The source is formed beforehand at the bottom of the structure before the memory cell pillars are created. This preliminary formation of the source eliminates the need for subsequent pillar punch etch processes that would require precise alignment, thereby resolving the alignment precision issue while maintaining high memory density through vertical stacking
Solution Approach 2:
Instead of forming the source after creating the memory cell pillars (which would require pillar punch etch), the invention inverts the sequence by forming the source first at the bottom, then building the pillars around it. This reversal eliminates the alignment problem entirely
2Reliability
If pillar punch etch process is used to electrically connect channel regions to source, then electrical connection is achieved, but process complexity and alignment challenges increase
Solution Approach 1:
The source is formed in advance at the bottom of the structure before the memory cell pillars are constructed. This preliminary action ensures that when the pillars are formed around the source, electrical connection is automatically achieved without requiring additional pillar punch etch processes, thereby simplifying the overall process while maintaining reliable electrical connection
Solution Approach 2:
The invention extracts and eliminates the pillar punch etch process from the fabrication sequence by reforming the process flow to form the source first. This removal of the complex alignment-critical step reduces process complexity while maintaining electrical connection reliability through the alternative geometry
Data Source
AI summary
A method of forming a semiconductor device comprises forming sacrificial structures and support pillars. The sacrificial structures comprise an isolated sacrificial structure in a slit region and connected sacrificial structures in a pillar region. Tiers are formed over the sacrificial structures and support pillars, and a portion of the tiers are removed to form tier pillars and tier openings, exposing the connected sacrificial structures and support pillars. The connected sacrificial structures are removed to form a cavity, a portion of the cavity extending below the isolated sacrificial structure. A cell film is formed over the tier pillars and over sidewalls of the cavity. A fill material is formed in the tier openings and over the cell film. A portion of the tiers in the slit region is removed, exposing the isolated sacrificial structure, which is removed to form a source opening. The source opening is connected to the cavity and a conductive material is formed in the source opening and in the cavity. Semiconductor devices and systems are also disclosed.