3D NAND Source Support Structure for Mold Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in enhancing the degree of integration and reliability of two-dimensional non-volatile memory devices, which is limited by the cost and complexity of miniaturizing pattern formation, while three-dimensional memory devices offer a potential solution but require innovative structural designs to improve reliability and efficiency.
Innovation Solution
A semiconductor memory device with a substrate featuring a cell array, extension, and boundary regions, including a mold structure with stacked gate electrodes and insulating films, channel structures, dummy channel structures, and a source layer with a support structure to enhance integration and reliability, allowing for improved pattern formation and reduced stress on the mold structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar memory device architecture is used, then manufacturing process is simpler and easier to manufacture, but the degree of integration is limited and cannot be increased further
Solution Approach 1:
The patent transitions from a two-dimensional planar memory device architecture to a three-dimensional vertical architecture. The memory cells are stacked vertically with multiple layers of word lines, bit lines, and channel structures extending in the vertical direction, thereby increasing the degree of integration without requiring further miniaturization of the planar footprint.
2Quantity of substance
If three-dimensional memory device architecture is used, then the degree of integration is increased, but stress on the mold structure increases and reliability deteriorates
Solution Approach 1:
The patent divides the three-dimensional memory device into multiple independent layers and regions, including a cell array region, an extension region, and a boundary region. The mold structure is segmented into multiple gate electrode layers stacked vertically. This segmentation distributes the mechanical stress across multiple discrete structures rather than concentrating it in a single monolithic structure, thereby improving reliability while maintaining high integration.
Solution Approach 2:
The patent applies different structural configurations to different regions of the device. The extension region has a different layout and component arrangement compared to the cell array region, allowing optimization of each region for its specific function while managing overall stress distribution. The boundary region provides a transition zone that helps manage stress between different structural areas.
3Quantity of substance
If pattern miniaturization is pursued to increase integration, then the degree of integration increases, but expensive apparatuses are required and manufacturing cost increases
Solution Approach 1:
Instead of continuing to miniaturize patterns in the two-dimensional plane which requires increasingly expensive lithography equipment, the patent moves to a three-dimensional architecture where integration is achieved by stacking multiple layers vertically. This approach increases capacity without requiring further reduction of feature sizes, thereby avoiding the need for more expensive miniaturization apparatuses.
Data Source
AI summary
A semiconductor memory device comprises a substrate; a mold structure on the substrate; a plurality of channel structures extending in the mold structure; a source layer and a source sacrificial layer between the substrate and the mold structure, wherein the source sacrificial layer is spaced apart from the source layer; and a source support layer on the source layer and the source sacrificial layer, wherein the source support layer is between the source layer and the source sacrificial layer, wherein an upper surface of the source support layer includes first and second portions extending parallel to the substrate, and a third portion that connects the first and second portions, wherein a vertical distance from an upper surface of the source layer to the first portion is smaller than a vertical distance from an upper surface of the substrate to the second portion.