3D NAND Split Block Array for Higher Memory Density
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Solution Overview
Problem
Conventional 3D NAND memory devices face challenges in maximizing memory cell density due to underutilized silicon areas in the circuit under array (CUA) region, particularly around bit line exits, which are typically not used for memory cells.
Innovation Solution
Implementing a split block memory array configuration that utilizes the unused silicon area in the CUA region by positioning string drivers and bit line exits on the same side as the memory arrays, allowing for additional memory cells without increasing die size, thereby enhancing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D NAND memory devices use traditional memory array layouts, then manufacturing is simpler, but memory cell density is limited due to underutilized silicon area in CUA region
Solution Approach 1:
The patent divides the memory array into multiple blocks (first block and second block) with different configurations. The first block uses conventional layout while the second block utilizes the previously unused silicon area in the CUA region by positioning string drivers and bit line exits on the same side as the memory arrays. This segmentation allows the system to achieve higher memory cell density without requiring complete redesign of the entire array architecture.
2Quantity of substance
If additional memory cells are added in the CUA region, then memory density increases, but the layout design becomes more complex
Solution Approach 1:
The patent applies different layout strategies to different regions of the memory device. The first memory block maintains a conventional layout for ease of manufacturing, while the second memory block implements an optimized layout that utilizes the CUA region's silicon area. This local differentiation allows the system to achieve higher overall density without requiring complete redesign of the entire array, thus balancing manufacturing simplicity with density improvement.
Data Source
AI summary
An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.