3D NAND Memory With On-Die SRAM for High-Speed Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D memory devices face challenges with poor array efficiency, large die size, high cost, and limited input/output (I/O) speed due to peripheral circuits occupying significant space and thermal budget constraints, which hinder high-speed sequential programming and memory density.
Innovation Solution
A 3D memory device with integrated on-die static random-access memory (SRAM) that shares the same chip as peripheral circuits, allowing for high-speed read and write operations and enabling high-speed sequential programming by using SRAM as a cache or data buffer, thereby reducing the need for additional memory space and improving memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If peripheral circuits are integrated on the same chip as memory arrays in conventional 3D memory devices, then device functionality is achieved, but die size becomes large and manufacturing cost increases
Solution Approach 1:
The patent divides the memory device into separate components: a first semiconductor structure containing peripheral circuits and SRAM cells, and a second semiconductor structure containing 3D NAND memory strings. These are then bonded together through a bonding interface, allowing functional integration while maintaining separate fabrication processes and reducing overall die size.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by bonding the first semiconductor structure (with peripheral circuits) to the second semiconductor structure (with memory strings) through a bonding interface. This vertical integration reduces die area while maintaining functionality.
2Adaptability or versatility
If peripheral circuits occupy significant space on the chip, then all necessary functions can be implemented, but memory density is limited
Solution Approach 1:
The patent segments the device into a first semiconductor structure for peripheral circuits and a second semiconductor structure for memory arrays. This separation allows the memory structure to be optimized for density without being constrained by peripheral circuit requirements, thereby increasing overall memory density.
Solution Approach 2:
By stacking the memory strings vertically in the second semiconductor structure and bonding it to the peripheral circuit structure, the patent achieves high memory density in a compact footprint, effectively moving from two-dimensional to three-dimensional space utilization.
3Ease of manufacture
If conventional 3D memory architecture is used without on-die SRAM, then manufacturing is simpler, but I/O speed and throughput are limited
Solution Approach 1:
The patent merges SRAM cells with the peripheral circuits on the same first semiconductor structure (substrate level integration). This combination allows high-speed read and write operations through the SRAM cache while maintaining a unified fabrication process, thus improving I/O speed without significantly complicating manufacturing.
Solution Approach 2:
The SRAM cells act as an intermediary buffer between the external interface and the 3D NAND memory strings. Data is first read into or written from the SRAM cache, then transferred to or from the memory strings through the bonding interface, enabling high-speed sequential programming and improving overall throughput.
4Productivity
If additional memory space is allocated for buffering operations, then high-speed sequential programming is enabled, but chip area increases
Solution Approach 1:
The patent combines the buffering function with the peripheral circuit structure by integrating SRAM cells on the same substrate. This allows the buffer to be implemented within the existing chip area without requiring additional dedicated space, thus enabling high-speed sequential programming without increasing chip area.
Solution Approach 2:
The first semiconductor structure serves multiple functions: it contains peripheral circuits for control and addressing, integrates SRAM cells for high-speed buffering and caching, and provides the bonding interface for connection to memory strings. This multi-functionality eliminates the need for separate buffer structures, maintaining compact chip area while enabling high-speed operations.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
Embodiments of three-dimensional (3D) memory devices with a 3D memory device includes a first semiconductor structure having a peripheral circuit, an array of SRAM cells, and a first bonding layer having a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure having an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts and a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.