3D NAND Stack Bonding for Density and Read Reliability
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the area occupied by unit memory cells, prompting the need for three-dimensional stacking of memory cells, which requires improved structural reliability and manufacturing methods to enhance operational reliability.
Innovation Solution
A semiconductor device comprising a first semiconductor structure with a page buffer, peripheral circuit, bit line, and stack structure, and a second semiconductor structure with pass transistors and peripheral circuit, bonded together to optimize memory cell placement and data storage, featuring a stack with step structures and channel structures extending through the stack, and a manufacturing method to form these structures efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three dimensions to improve integration density, then the area occupied by unit memory cells is reduced, but structural reliability and operational reliability deteriorate
Solution Approach 1:
The semiconductor device is divided into multiple layers including a first semiconductor layer containing page buffers and bit lines, a memory cell array layer with stacked memory cells, and a second semiconductor layer containing read distillation circuits. This segmentation allows each layer to be optimized independently for both density and reliability, with the read distillation circuit layer providing error correction to enhance operational reliability without compromising integration density.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional stacking by vertically arranging memory cells in multiple layers. The memory cell array includes first memory cells in a first layer and second memory cells in a second layer, with word lines and bit lines extending through multiple levels. This dimensional change dramatically increases integration density while the inclusion of read distillation circuits addresses reliability concerns through error correction mechanisms.
2Quantity of substance
If memory cells are stacked in three dimensions to improve integration density, then the area occupied by unit memory cells is reduced, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming the first semiconductor layer with page buffers, constructing the memory cell array with vertical stacks, and adding the second semiconductor layer with read distillation circuits. This segmentation allows complex three-dimensional structures to be built incrementally using standard semiconductor fabrication techniques, managing manufacturing complexity while achieving high integration density.
Solution Approach 2:
The patent implements three-dimensional memory cell stacking by extending word lines and bit lines through multiple layers and forming memory cells at different vertical levels. The memory cell array includes first memory cells in a first layer and second memory cells in a second layer, connected through shared bit lines and controlled by word lines that span multiple levels. This approach achieves high integration density through vertical stacking while using conventional fabrication processes to manage manufacturing complexity.
3Reliability
If read distillation circuits are added to improve operational reliability, then error correction capability is enhanced, but the area occupied by peripheral circuits increases
Solution Approach 1:
The read distillation circuits are placed in a separate second semiconductor layer above the memory cell array, utilizing the vertical dimension rather than consuming additional planar area. This layering approach allows error correction functionality to be added without increasing the footprint of peripheral circuits, as the read distillation circuits share the same vertical space above the memory cells through three-dimensional integration.
Solution Approach 2:
The read distillation circuits are merged with the memory cell array structure by positioning them in the second semiconductor layer directly above the memory cells, with shared bit lines connecting both layers. This merging allows the read distillation functionality to be integrated into the existing memory structure without requiring separate peripheral circuit areas, enhancing operational reliability while minimizing additional area consumption.
Data Source
AI summary
A semiconductor device may include: first semiconductor structure including a page buffer, a first peripheral circuit, a bit line located on the page buffer, a stack located on the bit line and the stack including a) a step structure, b) a source structure located on the stack, and channel structures extending through the stack; and a second semiconductor structure bonded to the first semiconductor structure and the second semiconductor structure including a) a second peripheral circuit located to face the source structure and b) pass transistors located to face the step structure.