3D NAND Memory Stacked Structure Parasitic Capacitance Reduction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration levels and capacity while maintaining effective cell characteristics, particularly in three-dimensional configurations where parasitic capacitance and manufacturing complexity are concerns.
Innovation Solution
The semiconductor memory device employs a stacked structure with alternating first and second layers, where the second layer has a different material with lower permittivity, and a method of manufacturing that includes forming stepped portions and replacing sacrifice layers with insulating layers to reduce parasitic capacitance and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to raise integration level, then capacity and integration density are improved, but parasitic capacitance increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking, where multiple memory cell layers are stacked above each other in the vertical direction. This dimensional change enables significantly higher integration density while maintaining acceptable parasitic capacitance through optimized layer spacing and material selection.
Solution Approach 2:
The patent employs composite material structures including alternating high-k dielectric layers and low-k dielectric layers, metal interconnect layers with different conductivity, and semiconductor layers with varying doping characteristics. These composite materials enable simultaneous optimization of capacitance, conductivity, and structural integrity in the three-dimensional architecture.
2Quantity of substance
If memory cells are disposed three-dimensionally to raise integration level, then capacity and integration density are improved, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into multiple identical or similar memory cell layers stacked vertically, each layer containing word lines, bit lines, charge storage regions, and interconnect structures. This segmentation allows for modular manufacturing where the same process steps can be repeated for each layer, reducing overall manufacturing complexity despite the increased integration density.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked within a single integrated structure, with lower layers supporting upper layers. The interconnect lines and control gates are nested within and between the memory cell layers, creating a compact three-dimensional architecture that maximizes space utilization while maintaining manufacturability through systematic layer-by-layer construction.
3Object-affected harmful factors
If alternating first and second layers with different materials are used, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in material properties, specifically alternating between high-k dielectric materials and low-k dielectric materials in successive layers. The low-k layers are strategically positioned to reduce parasitic capacitance between conductive elements, while the high-k layers provide necessary insulation and charge storage functionality. This parameter variation in material selection enables capacitance control without requiring extreme manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and capacity of memory cells while minimizing parasitic capacitance and simplifying the manufacturing process, leading to improved cell characteristics and reduced manufacturing complexity.
Implementation Method 1
a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.
Data Source
AI summary
An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.