3D NAND Memory Layout With Stacked Peripheral Circuits
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Solution Overview
Problem
The challenge lies in reducing the planar area occupied by peripheral circuits in 3D memory devices while maintaining high voltage requirements, as scaling down transistor sizes increases costs and leakage current, and traditional CMOS technology nodes are not feasible for memory devices.
Innovation Solution
The solution involves stacking peripheral circuits in different planes vertically, with memory cell arrays and high-voltage peripheral circuits separated, allowing for increased vertical scaling and reduced chip size, using polysilicon layers and hybrid bonding technologies to facilitate interconnects and reduce fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor sizes are scaled down to reduce planar area, then chip size is reduced, but manufacturing cost increases and leakage current increases
Solution Approach 1:
The patent transitions from planar (2D) arrangement to three-dimensional (3D) stacking architecture. Peripheral circuits are placed in different planes vertically, with memory cell arrays separated from high-voltage peripheral circuits. This vertical stacking enables high integration without scaling down transistor dimensions, thereby avoiding increased manufacturing costs and leakage current while reducing the planar footprint.
2Area of moving object
If transistor sizes are scaled down to reduce planar area, then chip size is reduced, but leakage current increases
Solution Approach 1:
The patent employs vertical stacking in three dimensions, placing peripheral circuits in different planes. This approach reduces the planar area occupied by peripheral circuits without requiring transistor size reduction, thereby preventing the increase in leakage current that would result from scaling down transistor dimensions.
3Ease of manufacture
If traditional CMOS technology nodes are used, then manufacturing is easier, but high voltage requirements cannot be met
Solution Approach 1:
The patent segments the device into distinct components: memory cell arrays formed using standard CMOS technology and high-voltage peripheral circuits formed separately. This segmentation allows each part to be optimized independently - the memory cells use conventional processes while the peripheral circuits are designed specifically for high-voltage operation, achieving both ease of manufacture and high voltage capability.
Solution Approach 2:
The patent introduces polysilicon layers as intermediary elements to facilitate connections between the memory cell arrays and peripheral circuits. These polysilicon layers serve as conductive pathways that enable high-voltage signal transmission while isolating the standard CMOS process from high-voltage requirements, acting as a mediator between different voltage domains.
4Device complexity
If peripheral circuits are placed in the same plane as memory cell arrays, then device complexity is reduced, but chip size increases
Solution Approach 1:
The patent implements vertical stacking where peripheral circuits are positioned in different planes from the memory cell arrays. This three-dimensional arrangement reduces the planar chip size by utilizing the vertical dimension, while the modular stacked architecture actually simplifies the overall device structure by separating functional blocks into distinct layers that can be independently optimized and interconnected through standardized interfaces.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.