3D NAND Stair Portion Gradient Optimization
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Solution Overview
Problem
The existing semiconductor storage devices with three-dimensional non-volatile memory have inefficiencies in the stair-like structure design, leading to increased area occupancy and reduced miniaturization potential due to invalid areas and uneven gradients in stair portions.
Innovation Solution
The semiconductor storage device employs a stacked body with alternating conductive and insulating layers, featuring stair portions with specific gradients and step configurations, including a dummy stair portion with a steeper gradient and reduced length, to minimize area occupancy and enhance miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a stair-like structure is employed to lead out word lines in three-dimensional non-volatile memory, then the word lines can be connected to external terminals, but the area occupied by the stair-like structure increases
Solution Approach 1:
The patent applies different gradient characteristics to different portions of the stair-like structure. Specifically, the first stair portion has a first gradient while the second stair portion has a second gradient that is steeper than the first gradient. This local differentiation allows the structure to maintain functionality while reducing overall area occupancy, as the steeper gradient in the second portion compresses the horizontal space required.
Solution Approach 2:
The patent transitions from a conventional uniform stair structure to a multi-gradient stair structure by introducing varying slopes in different sections. This dimensional variation in the gradient parameter enables more efficient space utilization, allowing the word lines to be led out while occupying less planar area through optimized vertical-to-horizontal transition.
2Stability of the object's composition
If conventional stair portions are used in three-dimensional non-volatile memory, then the structure can support multiple memory layers, but invalid areas increase and miniaturization is reduced
Solution Approach 1:
The patent introduces a dummy stair portion with a third gradient that is steeper than both the first and second gradients. This local quality enhancement in the dummy portion allows for more aggressive space compression without affecting the functional integrity of the main stair portions, thereby reducing invalid areas and increasing the proportion of area available for memory cells.
Solution Approach 2:
The stair-like structure is segmented into multiple distinct portions (first stair portion, second stair portion, and dummy stair portion), each with independently optimized gradient characteristics. This segmentation allows each portion to serve specific functions while collectively minimizing the total area occupied by non-memory structures, thus improving the memory portion area ratio.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.